Designing for Performance

FPGA 2 | FPGA23000-14-ILT (v1.0)

Course Description

Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

Level: FPGA 2
Course Duration: 2 days
Price: $1400 or 14 Xilinx Training Credits
Course Part Number: FPGA23000-14-ILT
Who Should Attend?: FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools
Registration: Register online in our secure store

Prerequisites

  • Essentials of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
  • Intermediate HDL knowledge (VHDL or Verilog)
  • Solid digital design background

Recommended RELs (Recorded e-Learning)

  • Basic HDL Coding Techniques REL (Parts 1 and 2)
  • Power Estimation REL

Software Tools

  • ISE Design Suite: Logic or System Edition 14.1

Hardware

  • Architecture: 7 series FPGAs*
  • Demo board: Kintex™-7 FPGA KC705 board*

* This course focuses on the 7 series FPGA architectures. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the architectural features of the 7 series FPGAs
  • Create and integrate cores into your design flow by using the CORE Generator™ interface
  • Describe the clocking features of the 7 series FPGAs and how they can be used to improve performance
  • Increase performance by duplicating registers and pipelining
  • Increase system reliability by adding an appropriate synchronization circuit
  • Describe different synthesis options and how they can improve performance
  • Describe a flow for obtaining timing closure
  • Pinpoint design bottlenecks by using timing reports
  • Apply advanced timing constraints to meet your performance goals
  • Use advanced implementation options to increase design performance

Course Outline

Day 1

  • Review of Essentials of FPGA Design
  • Designing with FPGA Resources
  • CORE Generator Software System
  • Clocking Resources
  • Lab 1: Designing With FPGA Resources
  • FPGA Design Techniques
  • Synthesis Techniques
  • Lab 2: Synthesis Techniques

Day 2

  • Achieving Timing Closure
  • Lab 3: Review of Global Timing Constraints
  • Path-Specific Timing Constraints, Part 1
  • Path-Specific Timing Constraints, Part 2
  • Lab 4: Achieving Timing Closure
  • Advanced Implementation Options
  • Lab 5: Designing for Performance
  • Lab 6: FPGA Editor Demo (optional)
  • ChipScope Pro Software (optional)
  • Lab 7: ChipScope Pro Software (optional)

Lab Descriptions

  • Lab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool.  Instantiate these cores and other clock resources and implement the design.
  • Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results.
  • Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
  • Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.
  • Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and the multiple run feature.
  • Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.
  • Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.

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Scheduled FPGA Courses

DARPA PRIVATE--High-Level Synthesis with the Vivado HLS Tools-Dallas
September 13 - September 14: 09:00 am - 05:00 pm
v2017.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Designing FPGAs Using the Vivado Design Suite 1-Dallas
September 27 - September 28: 09:00 am - 05:00 pm
This course offers introductory training on the Vivado Design Suite and helps you to understand the...

C-Based Design: High-Level synthesis with the Vivado HLx Tool
October 10 - October 11: 09:00 am - 05:00 pm
v2017.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.