Designing FPGAs Using the Vivado Design Suite 2

FPGA 2 | FPGAVDES2-ILT (2016.3)

Course Description

This course shows your how to build an effective FPGA design using synchronous design techniques, using the Vivado IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

Level: FPGA 2

Course Duration: 2 days
Price: $1400 or 14 Xilinx Training Credits
Course Part Number: FPGA-VDES2-ILT
Who Should Attend?:Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs.
Registration: Register online in our secure storeRequest a Class | FTL


  • Designing FPGA's Using the Vivado Design Suite 1 course
  • Working HDL knowledge (VHDL or Verilog)
  • Digital design experience

Optional Videos

  • Basic HDL Coding Techniques

Software Tools 

  • Vivado System Edition 2016.3


  • Architecture: UltraScale and 7 series FPGA's*
  • Demo board(optional): Kintex-7 FPGA KC705 board*

* This course focuses on the 7 series architecture. Contact us for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Create a Tcl script to create a project, add sources, and implement a design
  • Describe and use the clock resources in a design
  • Build resets into your system for optimization reliability and design speed
  • Take advantage of the Xilinx UltraScale FPGA resources
  • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
  • Use the Vivado IP integrator to create a block design
  • Create and package your own IP and add to the Vivado IP catalog to reuse
  • Describe the HLx design flow that increase productivity
  • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
  • Identify synchronous design techniques
  • Describe how an FPGA is configured

Course Outline

Day 1

  • UltraFast Design Methodology Introduction (Lecture)
  • Scripting in a Vivado Design Suite Project-Based Flow (Lecture,Lab)
  • Clocking Resources (Lecture,Lab)
  • Synchronous Design Techniques (Lecture)
  • Register Duplication (Lecture)
  • Resets (Lecture,Lab)
  • I/O Logic Resources (Lecture)
  • Timing Summary Report (Lecture,Demo)
  • Generated Clocks (Lecture,Demo)
  • Clock Group constraints (Lecture,Demo)
  • Introduction to Timing Exceptions (Lecture,Lab,Demo)

Day 2

  • Creating and Packaging Custom IP (Lecture,Lab)
  • Using an IP Container (Lecture,Demo)
  • Designing with IP Integrator (Lecture,Lab,Demo,Case Study)
  • Introduction to the HLx Design Flow(Lecture,Lab,Demo)
  • Configuration Process (Lecture)
  • Sampling and Capturing data in Multiple Clock Domains(Lecture,Lab)
  • Design Analysis Using Tcl Commands (Lecture,Demo,Lab)
  • Power Analysis and Optimization Using the Vivado Design Suite (Lecture,Lab)

Topic Descriptions

Day 1

  • UltraFast Design Methodology Introduction-Overview of the methodology guidelines covered in this course.
  • Scripting in a Vivado Design Suite Project Mode-Explains how to write Tcl commands in the project-based flow for a design.
  • Clocking Resources-Describes various clock resources, clocking layout, and routing in a design.
  • Synchronous Design Techniques-Introduces synchronous design techniques used in a FPGA design.
  • Register Duplication-Use register duplication to reduce high fanout nets in a design.
  • Resets-Investigates the impact of using asynchronous resets in a design.
  • I/O Logic Resources-Overview of I/O resources and the IOB property for timing closure.
  • Timing Summary Report-Use the post-implementation timing summary report to sign-off criteria for timing closure.
  • Generated Clocks- Use the report clock networks report to determine if there are any generated clocks in a design.
  • Clock Group Constraints-Apply clock group constraints for asynchronous clock domains.
  • Introduction to Timing Exceptions-Introduces timing exception constraints and applying them to fine tune design timing.

Day 2

  • Creating and Packaging Custom IP-Create your own IP and package and include it in the Vivado catalog.
  • Using an IP Container-Use a core container file as a single representation for an IP.
  • Designing with IP Integrator-Use the Vivado IP integrator to create the uart_led_sub-system.
  • Introduction to the HLx Design Flow-Use the HLx design flow to increase productivity and reduce run time when designing and verifying a design.
  • Configuration Process-Understand the FPGA configuration process, such as device power up, CRC check,etc.
  • Sampling and Capturing Data in Multiple Clock Domains- Overview of debugging a design with multiple clock domains that require multiple ILAs.
  • Design analysis Using Tcl Data Structures-Analyze a design using Tcl commands.
  • Power Analysis and Optimization Using the Vivado Design Suite-Use report power commands to estimate power consumption.

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Scheduled FPGA Courses

Essential Tcl Scripting for Vivado Design Suite
March 06 - March 07: 09:00 am - 05:00 pm
v2015.1  Learn how to use basic Tcl syntax and language structures to build scripts suitable...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.