Vivado Design Suite Hands-on Introductory Workshop

Vivado Design Suite Hands-on Introductory Workshop

FPGA 2 | VIVA12000-ILT (v1.0)

Course Description

This course offers an introductory training on the Vivado Design Suite.  This course is for experienced ISE software customers who want to take full advantage of the Vivado feature set.   Learn about the Vivado Design Suite projects, design flow, Xilinx Design Constraints (XDC) and basic timing reports.

Level: FPGA 2
Course Duration: 1 day
Price: $700 or 7 Xilinx Training Credits
Course Part Number: VIVA12000-ILT
Who Should Attend?: Existing Xilinx ISE software Project Navigator FPGA designers
Registration: Register online in our secure store

Prerequisites

  • FPGA design experience
  • Completion of the Essentials of FPGA Design or equivalent knowledge of Xilinx ISE® software implementation tools
  • Intermediate VHDL or Verilog knowledge

Recommended

Software Tools

  • Vivado System Edition 2013.2

Hardware

  • Architecture: 7 series FPGAs*
  • Demo board: Kintex™-7 FPGA KC705 board*

* This course focuses on the 7 series architecture. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Use the New Project wizard to create a new Vivado IDE project
  • Describe the supported design flows of the Vivado IDE
  • Generate a DRC report to detect and fix design issues early in the flow
  • Use the vivado IDE I/O Planning layout to perform pin assignments
  • Explore synthesis and implementation options and directives
  • Synthesize and implement the HDL design
  • Use the "baselining" process to gain timing closure on the design
  • Generate the various reports at syntheses and implementation by using the TcL Console and Flow Navigator to analyze the design
  • Use the Schematic and Hierarchy viewers to analyze and cross probe the design
  • Use the Vivado IDE IP flow to customize IP and generate the output products
  • Differentiate between the XCI and DCP files in the Vivado IDE IP flow

Course Outline

  • Vivado Synthesis and Implementation
  • Performing Baselining
  • Vivado Design Flows
  • Demo: Vivado IDE Overview
  • Lab 1: Vivado IDE Overview
  • Demo: Vivado DRC, Synthesis, and Implementation
  • Lab 2: Vivado Synthesis and Implementation
  • Lab 3: Vivado Design Rule Checker
  • Demo: Vivado Reports
  • Lab 4: Vivado Reports
  • Demo: Basic Design Analysis
  • Lab 5: Basic Design Analysis
  • Demo: Designing with the IP Integrator
  • Lab 6: Designing with IP

Lab Descriptions

  • Lab 1: Vivado IDE Overview – Create a project by using the New Project wizard in the Vivado IDE. Add files to the project by using the Add Sources wizard. Explore the Project Manager and Flow Navigator and simulate the design. Review the options available in the Flow Navigator.
  • Lab 2: Vivado Synthesis and Implementation – Make timing constraints according to the design scenario. Modify synthesis and implementation settings. Synthesize and implement the design. Generate and download the bitstream to the demo board.
  • Lab 3: Vivado Design Rule Checker- Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations.
  • Lab 4: Vivado Reports- Generate the Timing Summary report and Clock Networks report on the synthesized design. Review the contents of the Timing Summary, Utilization, and Check Timing reports after implementing the design.
  • Lab 5: Basic Design Analysis- Synthesize the design and use the Schematic and Hierarchy viewers to analyze the design. Implement the design and analyze some timing-critical paths with the Schematic viewer.
  • Lab 6: Designing with IP- Generate an IP from the Vivado IP catalog. Customize and generate the output products for the IP. Review the DCP and XCI files. Instantiate the IP in the design.

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Scheduled FPGA Courses

Designing FPGAs Using the Vivado Design Suite 1-Dallas
September 07 - September 08: 09:00 am - 05:00 pm
This course offers introductory training on the Vivado Design Suite and helps you to understand the...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.