Vivado Design Suite for ISE Project Navigator Users

FPGA 2 | VIVA10000-ILT (v1.0)

Course Description

This course offers an introductory training on the Vivado Design Suite.  This course is for experienced ISE software customers who want to take full advantage of the Vivado feature set.   Learn Vivado Design Suite projects, design flow, timing constraints, and timing reports.

Level: FPGA 2
Course Duration: 1 day
Price: $700 or 7 Xilinx Training Credits
Course Part Number: VIVA10000-ILT
Who Should Attend?: Existing Xilinx ISE software Project Navigator FPGA designers
Registration: Register online in our secure store

Prerequisites

Recommended

Software Tools

  • Vivado System Edition 2015.1

Hardware

  • Architecture: UltraScale FPGAs*
  • Demo board: Kintex™UltraScale KCU105 evaluation board*

* This course focuses on the 7 series architecture. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Use the Project Manager to start a new project
  • Identify the Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize a systematic approach to apply timing constraints and achieve timing  closure.
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

Course Outline

  • Design Methodology Summary
  • Introduction to the Vivado Design Suite
  • Vivado Design Flows
  • Lab 1: Vivado Tool Overview
  • Visualization for Analysis
  • Designing with IP
  • Demo: IP Flow
  • Demo: Designing with IPI
  • Basic Timing Constraints and STA
  • Demo: Reading Synthesis and Implementation Reports
  • Lab 2: Vivado Synthesis, Implementation and Timing Closure
  • Appendix: Visualization for Analysis
  • Appendix: Designing with IP
  • Appendix: Using the Pin Planning Environment

Lab Descriptions

  • Lab 1: Vivado Tool Overview – Create a project in the Vivado Design Suite. Add files, simulate, and elaborate the design. Review the available reports, analyze the design with the Schematic and Hierarchy viewers, and run a design rule check (DRC). Finally, assign some of the I/O pins using the IO Planner.
  • Lab 2: Vivado Synthesis, Implementation and Timing Closure – Synthesize and analyze the design with the Schematic viewer. Utilize a systematic approach to apply timing constraints and achgieve timing closure (i.e., understand the Xilinx baselining  recommendation). Run basic static timing analysis using the check_timing and report_clock_utilization reports. Implement the design and analyze some timing critical paths with the Schematic viewer. Download the bitstream to the demonstration board.

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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.