Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Users

FPGA 2 | VIVA11000-ILT 

Course Description

This course will update experienced ISE® software users to utilize the Vivado™ Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.

You will also learn to make path-specific, false path, and min/max timing constraints, as well as learn about timing constraint priority in the Vivado timing engine. Finally, you will learn about the scripting environment of the Vivado Design Suite and how to use the project-based and non-project batch flows.

You will also learn the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast design methodology case study. The UltraFast design methodology checklist is also introduced.

Level: FPGA 2
Course Duration: 3 days
Price: $2100 or 21 Xilinx Training Credits
Course Part Number: VIVA11000-ILT
Who Should Attend?: Existing Xilinx ISE Design Suite FPGA designers
Registration: Register online in our secure store

Prerequisites

Recommended

Software Tools

  • Vivado System Edition 2015.1

Hardware

  • Architecture: UltraScale FPGAs*
  • Demo board: None*

* This course focuses on the UltraScale series architecture. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Access primary objects from the design database and filter lists of objects using properties
  • Describe setup and hold checks and describe the components of a timing report
  • Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
  • Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
  • Describe all of the options available with the report_timing and report_timing_summary commands
  • Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
  • Analyze a timing report to identify how to center the clock in the data eye
  • Create scripts for the project-based and non-project batch design flows
  • Describe the UltraFast design methodology checklist
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Define a properly constrained design
  • Optimize HDL code to maximize the FPGA resources that are infered and meet your performance goals
  • Build resets into your system for optimum reliability and design speed
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Identify timing closure techniques using the Vivado Design Suite
  • Describe how the Xilinx design methodology techniques work effectively through case study/lab experience

Course Outline

Day 1

  • Vivado IDE Review
  • Accessing the Design Database
  • Demo: Finding Objects
  • Demo: Object Properties
  • Demo: Object Connectivity
  • Lab 1: Vivado IDE Database
  • Static Timing Analysis and Clocks
  • Demo: Generated Clocks
  • Lab 2: Vivado IDE Clocks
  • Inputs and Outputs
  • Lab 3: I/O Constraints
  • Timing Exceptions

Day 2

  • Lab 4: Timing Exceptions
  • Advanced Timing Analysis
  • Demo: Timing Reports
  • System-synchronous and Source-Synchronous I/O timing
  • Demo: System-synchronous I/O Timing
  • Lab 5: Advance I/O Timing
  • Vivado Design Suite Projects and Project-Based Scripting
  • Lab 6: Scripting in the Project-Based Flow
  • Appendix: vivado IDE Review
  • Appendix: Handling Vivado  Design Suite Objects in the GUI

Day 3

  • UltraFast Design Methodology Case Study
  • Demo: UltraFast Design Methodology Checklist
  • UltraFast Design Methodology
  • HDL Coding Techniques
  • Reset Methodology
  • Lab 7: Resets
  • Lab 8: SRL and DSP Inference
  • Synchronization Circuits and Reports
  • Timing Closure
  • Demo: Performance Baselining
  • Timing Closure and Design Conversion Lab Introduction
  • Lab 9: Timing Closure and Design Conversion
  • Appendix: Pipelining lab
  • Appendix: Synchronization Circuits and Reports
  • Appendix: Replication, Fanout, and Physical Optimization

 

 

Lab Descriptions

  • Lab 1: Vivado IDE Database – Utilize the Vivado IDE database to set properties on a design.
  • Lab 2: Vivado IDE Clocks  ndash; Create complete XDC constraints for the clocking resources in a design. Implement the design and use the available clocking reports to verify results. Understand the first step in the Xilinx baselining recommendation.
  • Lab 3: I/O Constraints ndash: Create input and output constraints for a source-synchronous design by using the Timing Constraints utility. You will aslo generate useful timing reports to verify the timing results. Understand the second step in the baselining recommendation.  
  • Lab 4: Timing Exceptions ndash; Using the Timing Constraints window to enter timing exceptions in the XDC format. You will also generate a useful timing report to verify the timing results. Understand the third step and last step in the baselining recommendation.
  • Lab 5: Advanced I/O Timing ndash; Make I/O timing constraints for a source-synchronous, double data rate (DDR) interface.Perform a static timing analysis of the interfaces to determine the optimal clock and data relationship for the maximum setup and hold-time margin. Finally adjust the data path delay to realize the optimal timing solution.
  • Lab 6: Scripting in the Project-Based Flow ndash; Write Tcl commands in the project-based flow for the design process ( from creating a new project through implementation).
  • Lab 7: Resets ndash: Investigate the proper design and use of resets. Examine the impact of seeing a design built originally with asynchronous resets, having resets removed, and finally with synchronous resets only used where necessary.
  • Lab 8: SRL and DSP Inference ndash; Evaluate the implementation results of a design that uses asynchronous resets and infers more dedicated hardware resources when resets are selectively removed from the design. You will also learn how to infer the DSP hardware resources for the common functions required by most FPGA designs.
  • Lab 9: Timing Closure and Design Conversion ndash; Learn how a generic processor design was optimized for the 7 series device architecture with basic design changes that impacted hardware usage, design speed, and the device utilization.

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Scheduled FPGA Courses

Essential Tcl Scripting for Vivado Design Suite
March 06 - March 07: 09:00 am - 05:00 pm
v2015.1  Learn how to use basic Tcl syntax and language structures to build scripts suitable...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.