Designing with the UltraScale and UltraScale+ Architectures

UltraScale and UltraScale+ Architectures Workshop


Course Description

This course is a one-day version of the Designing with the UltraScale Architecture course and introduces new and experienced designers to the most sophisticated aspects of the UltraScale and UltraScale+ architectures. Targeted towards designers who have used the Vivado Design Suite, this course focuses on designing for the new and enhanced resources found in our newest FPGA family.

Topics covered include an introduction to the clock management resources (MMCM and PLL), global and regional clocking resources, memory resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.

In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

Level: FPGA 3
Course Duration: 1 days
Price: $700.00 or 7 Xilinx Training Credits
Course Part Number: FPGA-US1D-ILT 
Who Should Attend?:  Anyone who would like to build a design for the UltraScale device family. 
Registration: Register online in our secure store


  • Completion of Essentials of FPGA Design and Vivado Design Suite STA and Xilinx Design Constraints course
  • OR completion of the Vivado Advanced XDC & STA for ISE Users course

Software Tools

  • Vivado Design or System Edition 2016.1


  • Architecture: UltraScale FPGA's
  • Demo board: None

* This course focuses on the UltraScale and UltraScale+ architectures. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Take advantage of the primary UltraScale architecture resources
  • Define the block RAM, FIFO, and DSP resources available for UltraScale FPGAs
  • Describe the UltraRAM features
  • Properly design for the I/O block and SERDES resources
  • Identify the MMCM, PLL, and clock routing resources included with the UltraScale architecture
  • Identify the hard IP resources available for implementing high-performance DDR4 physical layer interfaces
  • Describe the additional features of the dedicated transceivers
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1

  • Clocking Resources
  • Lab 1: Clocking Resources
  • Memory Resources
  • Lab 2: DDR4 MIG Design Creation
  • I/O Resources
  • Lab 3: SelectIO Design (Component Mode)
  • FPGA Design Migration
  • Lab 4: QSGMII Design Migration
  • Transceiver Overview
  • Lab 5: Transceiver Core Resources

Lab Descriptions

  • Lab 1: Clocking Resources-- Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.
  • Lab 2: DDR4MIG Design Creation--Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility.
  • Lab 3: SelectIO Design (Component Mode)--Implement a high-performance, source-synchronous interface using the UltraScale architecture SelectIO in component mode.
  • Lab 4: QSGMII Design Migration--Migrate an existing 7 Series QSGMII example design to a Kintex UltraScale architecture-based device. This lab will show you how to update your port connections and use the optimum logic resources available.
  • Lab 5: Transceiver Core Resources--Use the Transceiver Wizard to build a deign that uses a single transceiver and observe the file structures created.

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Scheduled FPGA Courses

Designing FPGAs Using the Vivado Design Suite 1-Dallas
April 10 - April 11: 09:00 am - 05:00 pm
This course offers introductory training on the Vivado Design Suite and helps you to understand the...

C-Based Design: High-Level synthesis with the Vivado HLx Tool
April 25 - April 26: 09:00 am - 05:00 pm
v2017.1 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.