UltraScale and UltraScale+ Architectures Workshop

UltraScale and UltraScale+ Architectures Workshop

FPGA-US1D-ILT

Course Description

This course is a one-day version of the Designing with the UltraScale Architecture course and introduces new and experienced designers to the most sophisticated aspects of the UltraScale and UltraScale+ architectures. Targeted towards designers who have used the Vivado Design Suite, this course focuses on designing for the new and enhanced resources found in our newest FPGA family.

Topics covered include an introduction to the clock management resources (MMCM and PLL), global and regional clocking resources, memory resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.

In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

Level: FPGA 3
Course Duration: 1 days
Price: $700.00 or 7 Xilinx Training Credits
Course Part Number: FPGA-US1D-ILT 
Who Should Attend?:  Anyone who would like to build a design for the UltraScale device family. 
Registration: Register online in our secure store

Prerequisites

 

  • Designing FPGAs Using the Vivado Design Suite 1 course 
  • Intermediate VHDL or Verilog knowledge 

 

 

Software Tools

  • Vivado HL Design or System Edition 2017.3

Hardware

  • Architecture: UltraScale and UltraScale FPGA's
  • Demo board: None

* This course focuses on the UltraScale and UltraScale+ architectures. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Take advantage of the primary UltraScale architecture resources
  • Define the block RAM, FIFO, and DSP resources available for UltraScale FPGAs
  • Describe the UltraRAM features
  • Properly design for the I/O block and SERDES resources
  • Identify the MMCM, PLL, and clock routing resources included with the UltraScale architecture
  • Identify the hard IP resources available for implementing high-performance DDR4 physical layer interfaces
  • Describe the additional features of the dedicated transceivers
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

  • UltraScale Architecture Clocking Resources {Lectures, Lab} 
  • FPGA Design Migration {Lecture, Lab} 
  • UltraScale Architecture Block Memory Resources {Lecture} 
  • UltraScale Architecture FIFO Memory Resources {Lecture} 
  • UltraRAM Memory {Lecture, Lab} 
  • DDR4 Design Creation Using MIG {Lab} 
  • UltraScale Architecture I/O Resources Overview {Lecture} 
  • UltraScale Architecture I/O Resources – Component Mode {Lecture, Lab} 
  • UltraScale Architecture I/O Resources – Native Mode {Lecture, Lab} 
  • UltraScale Architecture Transceivers {Lecture} 
  • UltraScale FPGAs Transceivers Wizard {Lecture, Lab} 

Topic Descriptions

 

  • UltraScale Architecture Clocking Resources – Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks. 
  • FPGA Design Migration – Migrate an existing 7 series design to the UltraScale architecture. 
  • UltraScale Architecture Block RAM Memory Resources –  Review the block RAM resources in the UltraScale architecture. 
  • UltraScale Architecture FIFO Memory Resources – Review the FIFO resources in the UltraScale architecture. 
  • UltraRam Memory – Use UltraRAM for a design requiring a larger memory size than block RAM. 
  • DDR4 MIG Design Creation – Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility. 
  • UltraScale Architecture I/O Resources Overview – Provides an overview of the I/O resources in the UltraScale architecture. 
  • UltraScale Architecture I/O Resources - Component Mode – Implement a high-performance, source-synchronous interface using I/O resources in Component mode for the UltraScale architecture. 
  • UltraScale Architecture I/O Resources - Native Mode – Implement a high-performance, source-synchronous interface using I/O resources in Native mode for the UltraScale architecture. 
  • UltraScale Architecture Transceivers – Review the enhanced features of the transceivers in the UltraScale architecture. 
  • UltraScale FPGAs Transceivers Wizard – Use the Transceivers Wizard to build a design that uses a single serial transceiver and observe the created file structures. 

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Scheduled FPGA Courses

Designing FPGAs Using the Vivado Design Suite 4
November 29 - November 30: 09:00 am - 05:00 pm
This course tackles the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware....

C-Based Design: High-Level synthesis with the Vivado HLx Tool
January 15 - January 16: 09:00 am - 05:00 pm
v2018.2 This course provides a through introduction to the Vivado High-Level Synthesis (HLS) tool....

Designing FPGAs Using the Vivado Design Suite 1-Longmont
January 17 - January 18: 09:00 am - 05:00 pm
This course offers introductory training on the Vivado Design Suite and helps you to understand the...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.