Introduction to the Zynq All Programmable SoC Architecture

EMB HW&FW 3 | EMBD24010-14-ILT (v1.0)

Course Description

This course provides hardware and firmware engineers with the knowledge to effectively utilize a Zynq™ All Programmable System on a Chip (SoC). It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the integration of programmable logic (PL).

The course also details the individual components that comprise the PS, I/O peripherals, timers, and caching, as well as the DMA, interrupt, and memory controllers. Emphasis will be placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques.

Level: Embedded Hardware and Firmware 3
Course Duration: 1 days
Price: $700 or 7 Xilinx Training Credits
Course Part Number: EMBD24010-14-ILT
Who Should Attend?: Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq All Programmable SoC and programmable logic.
Registration: Register online in our secure store

Prerequisites

  • FPGA design experience
  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE® software implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience

Software Tools

  • Xilinx ISE® Design Suite: Embedded or System Edition 14.2

Hardware

  • Architecture: Zynq-7000 All Programmable SoC*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or Zed board*

* This course focuses on the Zynq-7000 All Programmable SoC. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)
  • Evaluate a processing system (PS) and programmable logic (PL) AXI interface
  • Identify the configuration options for the Zynq All Programmable SoC

Course Outline

  • Zynq All Programmable SoC Architecture Overview
  • Inside the Application Processor Unit (APU)
  • Processor Input/Output Peripherals
  • Lab 1: Building a Zynq System on a Chip
  • Zynq System Architecture Essentials
  • Zynq All Programmable SoC PS/PL AXI Ports
  • Lab 2: Integrating Programmable Logic on the Zynq All Programmable SoC
  • Zynq Device Configuration
  • Zynq All Programmable SoC Memory Resources
  • Lab 3: Running and Debugging a Linux Application on the Zynq All Programmable SoC

Lab Descriptions

  • Lab 1: Building a Zynq System on a Chip – Examine the process of using the PlanAhead™ and Xilinx Platform Studio (XPS) tools to create a simple processing system.
  • Lab 2: Using DMA on the Zynq All Programmable SoC – Experiment with effectively using the PS DMA controller to move data between DDRx memory and a custom PL peripheral.
  • Lab 3: Running Linux on the Zynq All Programmable SoC – Explore a software application executing under the Linux operating system on the Zynq All Programmable SoC.

PDF version of this page.

Enroll Now.

Scheduled Embedded Courses

Zynq UltraScale+MPSoC-System Architect-Dallas
August 29 - August 30: 09:00 am - 05:00 pm
v2016.3 This two-day online course is structured to provide system architects with an overview of...

Zynq UltraScale+MPSoC-Software Developer
August 31 - September 01: 09:00 am - 05:00 pm
v2016.3 This two-day course is structured to provide software designers with a catalog of OS...

Designing FPGAs Using the Vivado Design Suite 2
October 05 - October 06: 09:00 am - 05:00 pm
v2016.3 This course shows you how to build an effective FPGA design using synchronous design...

Zynq UltraScale+MPSoC-System Architect-Online
October 26 - October 27: 09:00 am - 05:00 pm
v2016.3 This two-day online course is structured to provide system architects with an overview of...

Designing FPGAs Using the Vivado Design Suite 3
November 08 - November 09: 09:00 am - 05:00 pm
This course demonstrated timing closure techniques, such are baselining, pipelining,synchronization...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.