Developing and Optimizing Applications Using the OpenCL Framework for FPGAs

Course Part Number-EMBD-OCLSDA-ILT

Course Description

Learn how to develop new applications written in OpenCL, C/C++, and RTL in the SDAccel™ development environment for use on Xilinx FPGAs. Porting existing applications is also covered.  This course also demonstrates how to debug and profile OpenCL code using the SDAccel development environment. In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources. 

Level: SDx 1

Course Duration: 2 day 

Price: $1400 or 14 Xilinx Training Credits
Course Part Number: EMBD-OCLSDA-ILT 
Who Should Attend?: Anyone interested in quickly adding hardware acceleration to a software system.


Registration: Register online in our secure store

Prerequisites

  •     Basic knowledge of C/C++

Software Tools

  • SDAccel deveolment environment 2016.2 and common build tools*

* This course focuses on the 7 series, UltraScale™, and UltraScale+™ architectures.. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. 

 Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training , you will have the necessary skills to:

  • Identify parallel computing applications suitable for accelerating on FPGAs 
  • Discover how the FPGA architecture lends itself to parallel computing 
  • Write OpenCL programs for FPGAs 
  • Examine the OpenCL execution model 
  • Analyze the OpenCL memory model 
  • Profile and debug OpenCL code using the SDAccel development environment 
  • Discover how to maximize performance in FPGA fabric 
  • Efficiently utilize FPGA memory resources 
  • Utilize the SDAccel development environment 
  • Rapidly develop FPGA applications using OpenCL
  • Port programs written in OpenCL for CPUs or GPUs to Xilinx FPGAs 

Course Outline

Day 1

  • Introduction to OpenCL 
  • Comparison of CPU, GPU, and FPGA Architectures 
  • OpenCL Support for Xilinx FPGAs 
  • FPGA Hardware Details 
  • Introduction to the OpenCL API 
  • Lab 1: Creating an OpenCL Program from Scratch 
  • OpenCL Execution Model 
  • Lab 2:  Vector Addition 
  • Memory Hierarchy 
  • Profiling and Debugging 
  • Lab 3: Pi by Monte Carlo Processes 
  • Optimization 
  • Lab 4: Maximizing Performance 
  • Lab 5: Optimizing Kernels 

Day 2

  • Using the SDAccel Development Environment: Coding, Compiling, Emulating, Profiling, and Debugging 
  • Lab 6: Profiling and Debugging Using the SDAccel Development Environment GUI 
  • Using Existing C/C++ Code as Kernels in OpenCL 
  • Lab 7: Optimizing C/C++ Code for OpenCL 
  • RTL IP as Kernels in OpenCL 
  • Lab 8: Using an RTL Kernel 

Lab Descriptions

  • Lab 1: Creating an OpenCL Program from Scratch – Provides an overview of OpenCL API, memory transfers, and kernel enqueuer operations. 
  • Lab 2:  Vector Addition – Learn how to execute parallel kernels. 
  • Lab 3: Pi by Monte Carlo Processes – Implement the Pi by Monte Carlo processes. 
  • Lab 4: Maximizing Performance – Use vector data types and increase bandwidth. 
  • Lab 5: Optimizing Kernels – Use loop unrolling and loop pipelining.  
  • Lab 6: Profiling and Debugging Using the SDAccel Development Environment GUI – Learn how to use interactive programming tools to improve performance and squash bugs. 
  • Lab 7: Optimizing C/C++ Code for OpenCL – Convert existing C/C++ code into a kernel that can be used by OpenCL. 
  • Lab 8: Using an RTL Kernel – Learn how to use existing, highly optimized IP in a new OpenCL application. 

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Scheduled Embedded Courses

Zynq UltraScale+MPSoC-System Architect-Longmont
July 31 - August 01: 09:00 am - 05:00 pm
This two-day online course is structured to provide system architects with an overview of the...

Embedded System Design
August 08 - August 09: 09:00 am - 05:00 pm
v2018.1 The course is designed to bring FPGA designers up to speed on developing embedded systems...

Zynq SoC System Architecture 2018.1
September 06 - September 07: 09:00 am - 05:00 pm
* This course focuses on the Zynq-7000 SoC. Check with your local Authorized Training Provider for...

Zynq UltraScale+MPSoC-Software Developer
September 11 - September 12: 09:00 am - 05:00 pm
v 2017.3 This two-day course is structured to provide software designers with a catalog of OS...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.