Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment 

Course Part Number-EMBD-OCLSDA-ILT

Course Description

This two-day course is structured to help you develop new or existing OpenCL™, C/C++, and RTL applications in the SDAccel™ development environment for use on Xilinx FPGAs. This course also demonstrates how to debug and profile OpenCL API code using the SDAccel development environment.  In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources. The focus is on utilizing the tools to accelerate a design at the system architecture level as well as optimize the accelerators.

Level: EMBD 2

Course Duration: 2 day 

Price: $1600 or 16 Xilinx Training Credits
Course Part Number: EMBD-OCLSDA-ILT 
Who Should Attend?: Anyone who needs to accelerate their software applications using FPGAs.


Registration: Register online in our secure store

Prerequisites

  •     Basic knowledge of  Xilinx FPGA architecture
  •     Comfort with the C/C++ programming language

Software Tools

  • SDx™ development environment 2017.4.op 

Hardware

 

  • Architecture: Xilinx Kintex® UltraScale™ FPGA 

 

 

After completing this comprehensive training, you will have the necessary skills to: 

  • Describe how the FPGA architecture lends itself to parallel computing 
  • Explain how the SDx development environment helps software developers to focus on applications 
  • Examine the OpenCL API execution model 
  • Analyze the OpenCL API memory model 
  • Create kernels from C, C++, OpenCL, or RTL IP (using the RTL Kernel Wizard) 
  • Apply host code optimization and kernel optimization techniques 
  • Move data efficiently between kernel and global memory 
  • Profile and debug OpenCL API code using the SDAccel development environment 

After completing this comprehensive training, you will have the necessary skills to: 

 

  • Describe how the FPGA architecture lends itself to parallel computing
  •  Explain how the SDx development environment helps software developers to focus on applications 
  • Examine the OpenCL API execution model 
  • Analyze the OpenCL API memory model 
  • Create kernels from C, C++, OpenCL, or RTL IP (using the RTL Kernel Wizard) 
  • Apply host code optimization and kernel optimization techniques 
  • Move data efficiently between kernel and global memory 
  • Profile and debug OpenCL API code using the SDAccel development environment 

 

 

Course Outline

Day 1

 

  • Introduction to the SDAccel Environment and OpenCL Framework {Lecture} 
  • SDx Tools Overview {Lecture, Lab} 
  • Makefile Flow {Lecture, Lab} 
  • Introduction to FPGAs {Lecture} 
  • OpenCL Framework Fundamentals 1 {Lecture} 
  • ▪OpenCL Framework Fundamentals 2 {Lecture, Lab} 
  • Synchronization {Lecture, Lab} 
  • Introduction to NDRanges {Lecture} 

Day 2

 

  • Working with NDRanges {Lecture, Lab} 
  • ▪Profiling {Lecture} 
  • Debugging {Lecture} 
  • Optimization Methodologies {Lecture} 
  • Memory Transfer Optimization Techniques {Lecture} 
  • Kernel Optimization Techniques {Lecture, Lab} 
  • Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators {Lecture, Lab} 

Topic Descriptions:

Day 1

 

  • Introduction to the SDAccel Environment and OpenCL Framework – Explains how software engineers and application developers can benefit from the SDAccel development environment and Open Computing Language (OpenCL) framework. 
  • SDx Tools Overview – Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code. 
  • Makefile Flow – Introduces the SDAccel environment makefile flow, where the user manages the compilation of host code and kernel(s).
  • Introduction to FPGAs {Lecture} – Describes fundamental information about FPGAs, which is required to guide the SDAccel tool to the best computational architecture for any algorithm. 
  • OpenCL Framework Fundamentals 1 – Describes OpenCL framework models such as the Platform model, Execution model, Memory model, and Programming model.  
  • OpenCL Framework Fundamentals 2 – Describes OpenCL framework components such as the OpenCL platform API, OpenCL run-time API, and OpenCL programming language. 
  • Synchronization – Describes OpenCL synchronization techniques such as events, barriers, blocking write/read, and the benefit of using out-of-order execution. 
  • Introduction to NDRanges – Explains the basics of NDRange (N dimensional range) and the OpenCL execution model that defines how kernels execute with the NDRange definition. 

 Day 2

 

  •  Working with NDRanges – Explains the host code and kernel code changes with respect to NDRange. Also explains how NDRange works and the best way to represent the work-group size for the FPGA architecture.
  • ▪ Profiling – Describes the different reports generated by the tool that help to optimize data transfer and kernel optimization.
  • ▪ Debugging – Explains the support for debugging host code and kernel code as well as tips to debug the system.
  • ▪ Optimization Methodologies – Describes the recommended flow for optimizing an application in the SDAccel environment.
  • ▪ Memory Transfer Optimization Techniques – Describes the various optimization techniques for data transfer between kernels and global memory. ▪ Kernel Optimization Techniques {Lecture, Lab} – Apply different techniques such as loop unrolling, pipelining, and DATAFLOW.
  • ▪ Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators {Lecture, Lab} – Describes how the SDAccel environment provides RTL kernel developers with a framework to integrate their hardware functions into an application running on a host PC connected to an FPGA via a PCIe® interface. 

 

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Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.