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Debugging Techniques Using the Chipscope Pro Tools

FPGA 2 | CSP22000-13-ILT (v1.0)

Course Description

As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScopeâ„¢ Pro tool solution helps minimize the amount of time required for verification and debug.

This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This Xilinx Chipscope training will provide hands-on labs that demonstrate how the tools can address advanced verification and debugging challenges.

Level: FPGA 2
Course Duration: 2 days
Price: $1200 or 12 Xilinx TCs
Course Part Number: CSP22000-13-ILT
Who Should Attend?:System and logic designers who want to minimize verification and debug time
Registration: Register online in our secure store

Prerequisites

Recommended RELs (Recorded e-Learning)

Software Tools

  • Xilinx ISE® Design Suite: Logic or System Edition 13.1
  • ChipScope Pro 13.1 software

Hardware

  • Demo board: Spartan-6 FPGA SP605 board*

After completing this comprehensive course, you will have the necessary skills to:

  • Identify each ChipScope Pro tool core and explain its purpose
  • Effectively utilize the ChipScope Pro Analyzer tool
  • Implement the ChipScope Pro tool using the CORE Generatorâ„¢, Core Inserter, and PlanAheadâ„¢ tool flows
  • Select effective test points in your design
  • Optimize design and core performance when ChipScope Pro tool cores are used
  • Execute various techniques for collecting data, including file storage, scripting, and building custom triggers

Course Outline

Day 1

  • How the ChipScope Pro Tool Works
  • Inserting the Cores – Inserter Flows: Core Inserter and the PlanAhead Software
  • Labs 1 and 2: Using the Inserter Tool from Project Navigator and Using the Inserter Tool from the PlanAhead software
  • Instantiating the Cores – The CORE Generator Tool Flow
  • Lab 3: Using the CORE Generator Tool from Project Navigator
  • Triggering and Storage
  • Visualizing Data – The ChipScope Pro Analyzer Tool
  • Lab 4: Triggering and Visualization in the Analyzer Tool

Day 2

  • Tips and Tricks
  • Lab 5: Tips and Tricks
  • Time for Timing
  • Video Demo – Area Groups for Isolation
  • Case Studies
  • Lab 6: FPGA Editor Support for the ChipScope Pro Tool
  • Scripting*
  • Lab 7: VIO Tcl Scripting*
  • Remote Access*
  • Lab 8: Remote Access*

* Check with your local ATP to confirm whether this content is included with your specific class.

Lab Descriptions

  • Labs 1 and 2: Using the Inserter Tool from Project Navigator (Lab 1) and Using the Inserter Tool from the PlanAhead Software (Lab 2) – Insert an ICON and ILA cores into an existing netlist and debug a common problem.
  • Lab 3: Using the CORE Generator Tool from Project Navigator – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the ChipScope Pro Analyzer tool.
  • Lab 4: Triggering and Visualization in the Analyzer Tool – Configure triggers and view captured data using the ChipScope Pro Analyzer tool.
  • Lab 5: Tips and Tricks – Keep time across multiple sample windows; sample across multiple time domains; and implement a complex custom (unconventional) trigger.
  • Lab 6: FPGA Editor Support for the ChipScope Pro Tool – Change the signals being sampled by an ILA without having to reimplement the design.
  • Lab 7: VIO Tcl Scripting – Configure automated analysis.
  • Lab 8: Remote Access – Use the ChipScope Pro Analyzer tool to configure an FPGA, set up triggering, and view the sampled data from a remote location.

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Scheduled FPGA Courses

Advanced Design with the PlanAhead Analysis and Design Tool v13.1
February 14 - February 15: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...

Advanced Design with the PlanAhead Analysis and Design Tool v13.1
February 23 - February 24: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...

Essentials of FPGA Design v13.3
February 28 : 09:00 am - 05:00 pm
Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx...

Designing for Performance v13.3
February 29 - March 01: 09:00 am - 05:00 pm
This course will help you create more efficient designs. This course can help you fit your design...

Advanced Design with the PlanAhead Analysis and Design Tool v13.1
March 27 - March 28: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.