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ISE Design Tool Flow

FPGA 1 | FPGA16000-13-ILT (v1.0)

Course Description

ISE Design Tool Flow provides the overall context and framework for the development cycle of FPGAs. For those uninitiated to FPGA design, this course will arm you with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design now.

The flow will take you from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Project Navigator tool are introduced.  

Level: FPGA 1
Course Duration: 1 day
Price: $600 or 6 Xilinx Training Credits
Course Part Number: FPGA16000-13-ILT
Who Should Attend?: Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the ISE® 13.3 design tools
Registration: Register online in our secure store

Prerequisites

  • Basic knowledge of the VHDL or Verilog language

Recommended RELs (Recorded e-Learning)

Software Tools

  • Xilinx ISE Design Suite: Logic or System Edition 13.3

Hardware

  • Architecture: 7 series FPGAs*
  • Demo board: None*

* This course focuses on the Spartan-6 and Virtex-6 architectures. Contact us for specifics or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

  • Outline a complete project planning process
  • Create a new Project Navigator project in the ISE software
  • Access and modify Xilinx Synthesis Technology (XST) synthesis options
  • Assign pin locations using the I/O Planner
  • Enter global clock constraints using the Xilinx Constraints Editor
  • Simulate a design using the ISim Simulator

Course Outline

  • Course Agenda
  • Project Planning
  • Projects in the Project Navigator
  • Lab 1: Projects in the Project Navigator
  • HDL Synthesis and XST
  • Lab 2: XST Synthesis Options
  • Constraints and the I/O Planner
  • Lab 3: I/O Pin Planning
  • ISim Simulator
  • Lab 4: ISim Simulator
  • Additional Features
  • Summary

Lab Descriptions

  • Lab 1: Projects in the Project Navigator – Gain comprehensive hands-on experience with the HDL flow in the ISE software. Create a new project, add source files, synthesize a design, and use the error navigation feature to fix your HDL code.
  • Lab 2: Synthesis Options – Modify XST synthesis properties, read synthesis reports to compare the synthesis results with the implemented results, and use the schematic viewer to evaluate the design.
  • Lab 3: I/O Pin Planning – Review demo board documentation to determine the finished pinout and use the PlanAheadâ„¢ tool to assign pin location constraints and set other pin attributes.
  • Lab 4: ISim Simulator – Use the project navigator to view an HDL testbench, use the ISim Simulator to run simulation view output waveforms, add signals, and change their viewed format.

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Scheduled FPGA Courses

Advanced Design with the PlanAhead Analysis and Design Tool v13.1
February 14 - February 15: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...

Advanced Design with the PlanAhead Analysis and Design Tool v13.1
February 23 - February 24: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...

Essentials of FPGA Design v13.3
February 28 : 09:00 am - 05:00 pm
Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx...

Designing for Performance v13.3
February 29 - March 01: 09:00 am - 05:00 pm
This course will help you create more efficient designs. This course can help you fit your design...

Advanced Design with the PlanAhead Analysis and Design Tool v13.1
March 27 - March 28: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.