Designing for Performance for CPLDs

Intermediate | CPLD23000-9-ILT (v1.0)

Course Description

Designing for Performance for CPLDs is an intermediate-level course that provides a comprehensive overview of the CPLD software flow. By applying the techniques presented in this course, you will be able to enhance design performance and make the best possible use of Xilinx CPLD architectures.

This course uses the ISEâ„¢ 9.1 software, including the Constraints Editor and Timing Analyzer. Other topics include understanding the CPLD logic engine, estimating power, and fitting difficult designs.

Level: Intermediate
Course Duration: 1 day
Price: $600 or 6 Xilinx Training Credits
Course Part Number: CPLD23000-9-ILT
Who Should Attend?: Digital designers who have working knowledge of basic HDL (VHDL or Verilog) and who have some experience designing with Xilinx CPLDs. Alternatively, those who have recently attended Fundamentals of CPLD Design.
Registration: Register online in our secure store

Prerequisites

• Basic HDL knowledge (VHDL or Verilog)
• Digital design knowledge and Xilinx CPLD experience
• Fundamentals of CPLD Design course or equivalent knowledge of CPLD architecture; Xilinx implementation software flow and options; global constraints, the Constraints Editor; and reading fitting and timing reports
• Some experience with the software tool flow and global timing constraints

Software Tools

• Xilinx ISE 9.1i