Advanced VHDL

FPGA 4 | LANG21000-13-ILT (v1.0)

Course Description

Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.

The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.

Level: FPGA 4
Course Duration: 2 days
Price: $1200 or 12 Xilinx Training Credits
Course Part Number: LANG21000-13-ILT
Who Should Attend?: VHDL users with intermediate knowledge of VHDL
Registration: Register online in our secure store

Prerequisites

Designing with VHDL course or equivalent knowledge of modeling, simulation, and RTL coding
At least six months of coding experience beyond an introductory course

Software Tools

Xilinx ISE® Design Suite: Logic or System Edition 13.3

Hardware

Architecture: N/A*
Demo board: None*

*This course does not focus on any particular architecture. Contact us for specifics or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

Write efficient and reusable RTL, testbenches, and packages
Create self-testing testbenches
Create realistic models
Use the text I/O capabilities of the VHDL language
Store simulation data dynamically
Create parameterized code for design reuse

Course Outline

Day 1

Review of Current Knowledge
Simulation Concepts
Advanced Data Types
Subprograms and Design Attributes
Lab 1: Flexible Functions
Access Type Techniques and Blocks
Lab 2: Linked Lists with Access Types
Utilizing File IO
Lab 3: TextIO Techniques

Day 2

Cool Stuff with VHDL
Lab 4: Creating Real-World Simulations
Supporting Multiple Platforms
Lab 5: Supporting Multiple Platforms
Non-Integer Numbers
Lab 6: Implementing Fixed and Floating Point Numbers
Course Summary

Lab Descriptions

Lab 1: Flexible Functions – Construct and use predefined attributes to build functions and procedures that automatically adjust to the size of the passed arguments as well as creating a reusable module with unconstrained ports.
Lab 2: Linked Lists with Access Types – Create linked lists to capture arbitrarily large data sets. Also included in this lab is a reusable helper package for managing singly linked lists.
Lab 3: TextIO Techniques – Load memory for synthesis via a text file using the TextIO extensions for std_logic and std_logic_vector as provided by the std_logic_TextIO package.
Lab 4: Creating Real-World Simulations – Create spread-spectrum clocks with jitter and other real-world factors. Model board and behavioral component delay.
Lab 5: Supporting Multiple Platforms – Effectively use configuration statements, conditional generates, and scripts to build variations on VHDL themes.
Lab 6: Implementing Fixed and Floating Point Numbers – Construct a simple fixed point math example and compare to the IEEE_PROPOSED fixed and floating point models.

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Scheduled Language Courses

Designing with VHDL v13.3
February 08 - February 10: 09:00 am - 05:00 pm
This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on...

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates. If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs. No obligation necessary.