Connect on LinkedIn
Connect on Facebook
Watch us on YouTube
Advanced FPGA Implementation
FPGA 4 | FPGA33000-13-ILT (v1.0)
Course Description
Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools.
This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the 7 series FPGAs.
Level: FPGA 4
Course Duration: 2 days
Price: $1200 or 12 Xilinx Training Credits
Course Part Number: FPGA33000-13-ILT
Who Should Attend?: Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity
Registration: Register online in our secure store
Prerequisites
- Essentials of FPGA Design
- Designing for Performance
- Intermediate knowledge of Verilog or VHDL is strongly recommended
- At least six months of design experience with Xilinx tools and FPGAs
Software Tools
- Xilinx ISE Design Suite: Logic or System Edition 13.3
Hardware
- Architecture: Xilinx 7 series FPGAs*
* This course focuses on the 7 series FPGA architectures. Contact us for the specifics of the in-class labs or other customizations.
After completing this comprehensive training, you will have the necessary skills to:
- Create and edit a User Constraint File (UCF)
- Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfaces
- Implement designs via the Tcl command line
- Use the PlanAheadâ„¢ tool to create area constraints
- Use design preservation techniques to simplify design ripple effects
- Change signals of interest in the ChipScopeâ„¢ Pro tool for board-level debugging using the FPGA Editor
Course Outline
- Introduction
- Lab 1: Timing Closure Review
- UCF Editing
- Lab 2: UCF Editing
- Advanced I/O Timing
- Lab 3: Adv I/O Timing
- Tcl Scripting
- Lab 4: Tcl Scripting
- Floorplanning an Effective Layout
- Lab 5: Floorplanning
- Design Preservation Techniques
- FPGA Editor: Viewing and Editing a Routed Design
- Lab 6: Advanced FPGA Editor
Lab Descriptions
- Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.
- Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.
- Lab 3: Adv I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.
- Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.
- Lab 5: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.
- Lab 6: Adv FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.
Scheduled FPGA Courses
Advanced Design with the PlanAhead Analysis and Design Tool v13.1
February 14 - February 15: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...
Advanced Design with the PlanAhead Analysis and Design Tool v13.1
February 23 - February 24: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...
Essentials of FPGA Design v13.3
February 28 : 09:00 am - 05:00 pm
Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx...
Designing for Performance v13.3
February 29 - March 01: 09:00 am - 05:00 pm
This course will help you create more efficient designs. This course can help you fit your design...
Advanced Design with the PlanAhead Analysis and Design Tool v13.1
March 27 - March 28: 09:00 am - 05:00 pm
Learn to increase design performance and achieve repeatable performance by using the PlanAheadâ„¢...
Alternative Dates and Locations
Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates. If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs. No obligation necessary.