Essentials of Xilinx FPGA Design Course

** This course focuses on the 7 series FPGA architecture. The labs which require a demo board are targeted to use the Spartan-6 FPGA SP605, Virtex-6 FPGA ML605 board, or Avnet LX9 microboard. Contact us for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

• Take advantage of the primary features of the 7 series FPGAs
• Use the Xilinx Project Navigator to implement and simulate an FPGA design
• Read reports and determine whether your design goals were met
• Use the Clocking Wizard to create MMCM instantiations
• Use the I/O Planner to make good pin assignments
• Use the Xilinx Constraints Editor to enter global timing constraints

Course Outline

• Course Agenda
• Basic FPGA Architecture
• Xilinx Tool Flow
• Lab 1: Xilinx Tool Flow
• Reading Reports
• Lab 2: Clocking Wizard and Pin Assignment
• Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool
• Global Timing Constraints
• Lab 4: Global Timing Constraints
• Synchronous Design Techniques
• Course Summary

Lab Descriptions

• Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to the evaluation board.
• Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAheadâ„¢ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.
• Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.
• Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.

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Scheduled FPGA Courses

Alternative Dates and Locations

Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates.  If there are no currently scheduled classes listed above or if none of the classes are convenient, please tell us what dates and locations will meet your needs.  No obligation necessary.