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Virtex 7 and the FM-S18


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: 27. 06. 2014 [15:20]
sapril
Topic creator
registered since: 27.06.2014
Posts: 2
Hello -

I am using a V7 development card with the FM-S18 which has been modified for 1.8V I/Os. This is noted by the white label on the board that reads, "1.8/2.5 VADJ".

The user guide states that for boards that have been modified to support 1.8 V the dip switch used to set the frequency is unreliable except for the setting 00 which corresponds to 212.5 MHz. In my design I need this to be 312.5 MHz and there does not seem to be a way to change it since the 10 GE interface is the only way that the host computer can reach the board. Are there any ways to work
around this? Is there a schematic available for the board?

Thanks,
Steve
: 27. 06. 2014 [16:12]
dlautzenheiser
registered since: 19.02.2009
Posts: 4
Steve,
The user manual for the FM-S18 explains how to program the clock generators from the host FPGA - see section 7.1.3. The clock generators are ALWAYS accessible from the host FPGA through their IIC interfaces on the LA00 and LA01 pairs of FMC pins (Table 7-4). Without knowing which V7 card you are using, we cannot tell which pins of the FPGA these would be. It is a pretty simple matter to drive the IIC interface from the FPGA using the guidelines in the User Manual. There is also a reference design supplied with the FM-S18 that can be used as a starting point although it is for the Xilinx ML605 development card.
If you need additional technical support, please email support(at)fastertechnology[dot]com
: 27. 06. 2014 [16:58]
sapril
Topic creator
registered since: 27.06.2014
Posts: 2
Hi - ok, then I would need to program the I2C controller automatically in hardware since the FMC is required to be up and running for host access. Sounds like a lot of work just to get the clock set up. I did notice in the latest user manual that the Rev C FMC has fixed this issue. I think I will ask for a replacement instead since I have four rev B FMCs.