IP Cores

Included with the P Series products, Faster Technology provides a library of high performance and infrastructure IP Cores to enable users to get a complete system up and running straight out of the box.  Complete reference designs that boot into Linux allow you to focus on your application, instead of the board programming environment.  A selection of infrastructure cores allow you to modify or expand the reference designs to meet the exact needs of your application. 

In addition, a subset of the following cores are available for use independently of the P Series under the Xilinx SignOnce IP Program.  Contact Faster Technology for more information.

PLB to DDR2 Core

This core provides a custom high performance PLB (Processor Local Bus) to DDR2 (Double Data Rate-2) interface to support the memory-centric architecture of the P Series products.  It allows the PLB bus to achieve high efficiency by supporting advanced features such as simultaneous reads and writes.

PLB to FSL IPIF Core

This core is designed to be a common front end to cores that process streaming data, such as many DSP (Digital Signal Processing) cores.  It provides a PLB DMA (Direct Memory Access) engine that understands circular buffers and is capable of performing maximum length deterministic burst transfers when combined with the FTL PLB DDR2 core. The user side interface of this core consists of up to eight FSL (Fast Simplex Link) buses in each direction.  Each of the FSL buses has its own DMA channel, and they run independently.  The PLB DMA engine is capable of performing simultaneous read and write transfers for high throughput.

PCI to PLB/OPB Core

The PCI (Peripheral Component Interconnect) core has a built-in DMA engine that supports master mode transactions on both the PLB and PCI buses.  The core will respond to PCI target transactions with corresponding master transactions on the OPB (On-chip Peripheral Bus) side.

Dual PLB to GigE Core

An embedded offload engine in the dual GigE (Gigabit Ethernet) core allows selected traffic to be offloaded from the Linux network stack running on the PowerPC.  The selected streams of data are sent via DMA to contiguous circular buffers in DDR2 memory.  The embedded offload engine is implemented in a Xilinx PicoBlazeTM soft processor and is programmed in assembly language.  The program for the offload engine is programmed by the PowerPC.  The supplied offload program is for the SDDS real time Signal Data Distribution System.  The SDDS protocol is wrapped in UDP/IP and is multi-cast over VLANs.

miniSD Core

The miniSD card that is used to configure the Virtex-4 is also available for use by the V4 after configuration.  A boot-loader program is supplied that can load and run a program or an operating system, such as Linux, from the miniSD card.  The miniSD card can also be mounted from Linux as a read/write FAT16 file system.

Re-sampler Core

This core is an asynchronous re-sampler or synchronous rate changer.  It understands the SDDS data format, and the supplied embedded Linux software uses the meta data embedded in the data stream to control the core.  Embedded SDDS time codes are re-calculated to account for the re-sampling that was performed.

DDC Core

This core can tune, filter and decimate a stream of data.  It also understands the SDDS format.  Embedded SDDS time codes are re-calculated to account for the processing that was performed.

FFT Core

This core performs FFTs (Fast Fourier Transforms) on blocks of streaming data.  It also understands the SDDS format.

SPI ROM Core

This core enables the SPI (Serial Peripheral Interface) ROM that contains the P Series board serial number, MAC (Media Access Control) IDs, and other build information to be mounted and read by software running in the embedded Linux environment.  The information in the SPI ROM is formatted as an XML file.

Pseudo SRAM Core

A Xilinx memory controller core from the EDK library is used to access the on-board PSRAM.  In systems running the embedded Linux operating system and communicating with the host system via the PCI interface, the PSRAM is reserved for this communication.

Serial Port Core

Two serial ports are provided utilizing Xilinx serial port cores from the EDK library.

GPIO Core

The GPIO core from the Xilinx EDK library is used to provide support for the on-board switches & LEDs.