Event

Title:

Advanced FPGA Implementation

Start date:

February 25

End date:

- February 26

Start time:

09:00 am

End time:

05:00 pm

Location:

Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244)

Registration:

Description:

Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 11.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 11.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.

After completing this comprehensive training, you will have the necessary skills to:

Create and edit a User Constraint File (UCF)
Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfaces
Implement designs via the Tcl command line
Preserve design results by using SmartGuide™ technology
Use the PlanAhead™ tool to create area constraints
Change signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor

Course Outline

Introduction
Lab 1: Timing Closure Review
UCF Editing
Lab 2: UCF Editing
Advanced I/O Timing
Lab 3: Advanced I/O Timing
Tcl Scripting
Lab 4: Tcl Scripting
SmartCompile™ Technology Design Preservation Techniques
Lab 5: SmartGuide Technology
Floorplanning an Effective Layout
Lab 6: Floorplanning
FPGA Editor: Viewing and Editing a Routed Design
Lab 7: Advanced FPGA Editor

Lab Descriptions
Note: Labs will be based on Xilinx ISE 11.1 software.

Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.
Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.
Lab 3: Advanced I/O Timing – Compose timing constraints for an I/O interface. Analyze the timing and determine changes to optimize the interface timing.
Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.
Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.
Lab 6: Floorplanning – Implement a design by using floorplanned constraints to enhance the timing results over a design without floorplanning.
Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.