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Event
Title:
Lunch-N-LearnStart date:
February 07Start time:
10:00 amEnd time:
12:00 pmLocation:
OnlineDescription:
Lunch-N-Learn Information and registration link on PDF Flyer "CLICK HERE"
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- Applications
- Products
- Training
- Training Value - Individuals
- Training Value - Employers
- Training Courses
- Vitis and PetaLinux Workshop
- Timing Closure
- Migrating from ISE & Spartan-6
- Developing AI Inference Solutions with the Vitis AI Platform
- kria SoM
- IP Integrator Tool
- Designing w/the DFX using Vivado Design Suite
- Versal ACAP PCIe
- Using Xilinx Alveo Cards
- Versal ACAP: Power & Board
- Vitis HLS Tool
- Versal Engine 3
- Versal ACAP: Network on Chip
- Versal ACAP Achitecture & Methodology
- Versal AI Engine 2
- Versal AI Engine 1
- Zynq UltraScale+ MPSoC 3
- Migrating to the Vitis Embedded Software Development IDE
- (Workshop) Embedded & Accelerated Applications w/ Vitis Unified Software
- Accelerating Applications with Vitis Unified Software Environment
- Zynq UltraScale RFSoC (3 day)
- Verification with SystemsVerilog
- Designing with SystemsVerilog
- Embedded Design with PetaLinux
- Zynq SoC System Architecture
- FPGA UltraFast Design Methodology
- UltraScale and UltraScale+ Series Families
- Serial Transceivers
- Zynq MPSoC System Architect-Online Custom
- Zynq UltraScale MPSoC Software Developer-Online Version
- Zynq UltraScale+ C/C++ SDSoC
- Zynq UltraScale+ MPSoC Hardware Designer
- Designing FPGAs Using the Vivado Suite 4
- Designing FPGAs Using the Vivado Suite 3
- Designing FPGAs Using the Vivado Suite 2
- Designing FPGAs Using the Vivado Suite 1
- Zynq MPSoC Software Developer
- Zynq UltraScale+ MPSoC System Architect
- UltraScale Series Families
- Vivado DS Advanced Workshop (custom)
- Vivado DS Workshop
- Essential Tcl Scripting
- Vivado for ISE Users
- Adv XDC and STA for ISE Users
- Designing with Xilinx AMS
- Essentials of FPGA Design
- Designing for Performance
- Advanced FPGA Implementation
- Spartan-6 and Virtex-6 Families
- 7 Series Families
- Essential Design with PlanAhead
- Advanced PlanAhead Design
- ISE Design Tool
- Xilinx Partial Reconfiguration
- FPGA Power Optimization
- Essentials of Microprocessors
- C Programming with SDK
- Embedded Systems in 1 Day
- Embedded Systems Design
- Advanced EDK
- EDK S/W Development
- Adv SDK Design
- Introduction to Zynq SoC
- Zynq All Programmable SoC
- EDK MicroBlaze Development
- EDK H/W Workshop
- EDK S/W Workshop
- Connectivity Systems in 1 Day
- PCIe Protocol Overview
- Integrated PCIe Systems
- Multi-Gigabit Serial I/O
- SI and Board Design
- H/S Memory Interface Design
- Ethernet MAC Controllers
- DSP System Generator
- DSP Implementation Techniques
- Vivado HLS - C-based Design
- Designing with Verilog
- Designing with VHDL
- Advanced VHDL
- L&L
- Online Xilinx Training
- Class Schedule
- Store
- Cores
- Services
- Development
- Support
- Log In
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9711 S Mason Rd, Suite 125, MB 109, Richmond, TX 77407 USA T:281.391.5482 F:281.391.9384