Event

Title:

UltraFast Design Methodology*Confirmed to run

Start date:

March 03

End date:

- March 04

Start time:

09:00 am

End time:

05:00 pm

Location:

Online

Registration:

Description:

This course describes the FPGA design best practices and skills to be successful using the Vivado® Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an FPGA design methodology case study. The UltraScale design metholology checklist is also introduced.

After completing this comprehensive training, you will have the necessary skills to:

Describe the UltraFast design metholology checklist
Identify key areas to optimize your design to meet your design goals and performance objectives
Define a properly constrained design
Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
Build resets into your system for optimum reliability and design speed
Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
Identify timing closure techniques using the Vivado Design Suite
Describe how the Xilinx design methodology techniques work effectively through case study/lab experience

Event

PDF Course Outline 2021.2