Event

*Confirmed to run! Designing FPGAs Using the Vivado Design Suite 2
July 08
- July 09
09:00 am
05:00 pm
Online
Register online in our secure store

This course shows you how to build an effective FPGA design using synchronous design techniques, using the Vivado IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

After completing this comprehensive training, you will have the necessary skills to:

• Build resets into your system for optimum reliability and design speed.
• Take advantage of the Xilinx UltraScale FPGA resources
• Build custom IP with the IP Library utility
• Apply basic timing constraints (create_clock,set_input_delay, and set_output_delay)
• Use  the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
• Identify synchronous design techniques
• Describe how an FPGA is configured

Course Outline

Day 1

• UltraFast Design Methodology Introduction 2 (Lecture,Lab)
• Scripting in a Vivado Design Suite Project-Based Flow (Lecture,Lab)
• Clocking Resources (Lecture,Lab)
• Synchronous Design Techniques (Lecture)
• Register Duplication (Lecture)
• Resets (Lecture,Lab)
• I/O Logic Resources (Lecture)
• Timing Summary Report(Lecture,Demo)
• Introduction to Timing Exceptions (Lecture,Lab,Demo)

Day 2

• Generated Clocks (Lecture,Demo)
• Applying Clock Groups Constraints (Lecture,Demo)
• Creating and Packaging Custom IP (Lecture,Lab)
• Using an IP Container (Lecture,Demo)
• Designing with IP Integrator (Lecture,Lab,Demo)
• Introduction to the HLx Design Flow (Lecture,Lab,Demo)
• Configuration Process (Lecture)
• Sampling and Capturing data in multiple clock-domains in VLA (Lecture,Lab)
• Design Analysis Using TCL Data Structures (Lecture,Lab)
• Power Analysis and Optimization Using the Vivado Design Suite (Lecture,lab)

Topic Descriptions

Day 1

• UltraFast Design Methodology Introduction 2-Overview of the methodology guidelines covered in the course.
• Scripting in a Vivado Design Suite Project-Based Flow-explains how to write Tcl commands in the project-based flow for a design.
• Clocking Resources-Describes various clock resources,clocking layout,and routing in a design.
• Synchronous Design Techniques- Introduces synchronous design techniques used in an FPGA design.
• Register Duplication-Use register duplication to reduce high fanout nets in a design.
• Resets-Investigates the impact of using asynchronous resets in a design.
• I/O logic Resources-Overview of I/O resources and the IOB property for timing closure.
• Timing Summary Report-Use the post-implementation timing summary report to sign-off criteria for timing closure.
• Introduction to Timing Exceptions-introduces timing exception constraints and applying them to fine tune design timing.

Day 2

• Generated Clocks-Use the Report clock networks report to determine if there are any generated clocks in a design.
• Apply Clocks Groups Constraints-Apply closk groups constrint for asynchronous clock domains.
• Creating and Packaging Custom IP-Create your own IP and package and include it in the Vivado IP catalog.
• Using an IP Container-Use a core container file as a single file representation of an IP.
• Designing with IP Integrator-Use the Vivado IP integrator to create the uart_led sub-system.
• Introduction to the HLx Design Flow- Use the HLx design flow to increase productivity and reduce run time when designing and verifying a design.
• Configuration Process-Understand the FPGA configuration process, such as device power up, CRC check, etc.
• Sampling and Capturing Data in Multiple Clock Domains in VLA-Overview of debugging a design with multiple clock domains that require multiple ILAs.
• Design Analysis Using Tcl Data Structures-Analyze a design using Tcl commands.
• Power Analysis and Optimization Using the Vivado Design Suite-Use report power commands to estimate consumption.

Register Today

Registration for this course is available through our Online Store.