Event

Title:

*Confirmed to Run! Zynq SoC System Architecture

Start date:

March 10

End date:

- March 11

Start time:

09:00 am

End time:

05:00 pm

Location:

Online

Registration:

Description:

* This course focuses on the Zynq-7000 SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. After completing this comprehensive training, you will have the necessary skills to:

Describe the architecture and components that comprise the Zynq SoC processing system (PS)
Relate a user design goal to the function, benefit, and use of the Zynq SoC
Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
Analyze the tradeoffs and advantages of performing a function in software versus PL

Course Outline

Day 1

Overview {Demo}
Application Processor Unit (APU) {Lab}
Neon Co-Processor
Input/Output Peripherals {Demo}
PS Peripherals

○ Low-Speed: Overview {Lab}

○ Low-Speed: UART {Demo}
○ Low-Speed: CAN {Demo}

○ Low-Speed: I2C

○ Low-Speed: SD/SDIO

○ Low-Speed: GPIO

○ High-Speed: USB

○ High-Speed: Gigabit Ethernet {Lab}

DMA Controller (DMAC) {Lab}
DMA

○ Introduction and Features

○ Block Design and Interrupts

○ Read and Write

Day 2

AXI
○ Introduction
○ Variations

○ Transactions {Demo, Lab}

PS-PL Interface {Demo, Lab}
Booting {Lab}
Memory Resources {Demo}
Meeting Performance Goals {Lab}
Hardware Design {Lecture}
Software Design {Demo, Lab}
Debugging {Lab}
Tools and Reference Designs

Topic Descriptions

Day 1

Overview – Provides a general overview of the Zynq SoC.
Application Processor Unit (APU) – Explores the individual components that comprise the APU. ▪ Neon Co-Processor – Describes the Neon co-processor that is the companion to each Cortex-A9 processor.
Input/Output Peripherals – Introduces the components that comprise the IOP block of the Zynq device PS.
Peripherals

○ Low-Speed: Overview – Introduces the low-speed peripherals in the Zynq SoC.

○ Low-Speed: UART – Introduces the UART low-speed peripheral.

○ Low-Speed: CAN – Introduces the CAN low-speed peripheral.

○ Low-Speed: I2C – Introduces the I2C low-speed peripheral.

○ Low-Speed: SD/SDIO – Introduces the SD/SDIO low-speed peripheral.

○ Low-Speed: GPIO – Introduces the GPIO low-speed peripheral.

○ High-Speed: USB – Introduces the USB high-speed peripheral.

○ High-Speed: Gigabit Ethernet – Introduces the Gigabit Ethernet high-speed peripheral.

DMA Controller (DMAC) – Explores the operation of the DMAC, which is located in the APU.
DMA

○ Introduction and Features – Introduces the direct memory access controller.

○ Block Design and Interrupts – Introduces the DMA block design and the DMA interrupts.

○ Read and Write – Introduces the concepts behind DMA reading and writing.

Day 2

○ Introduction – Introduces the AXI protocol.

○ Variations – Describes the differences and similarities among the three primary AXI variations.

○ Transactions – Describes different types of AXI transactions.

PS-PL Interface – Describes in detail the PS interconnect and how it affects PL architecture decisions.
Booting – Explains the boot process of the PC and configuration of the PL.
Memory Resources – Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS.
Meeting Performance Goals – Focuses on Zynq device performance, including DDR access from the PL, DMA considerations, and power control and reduction techniques.
Hardware Design – Discusses the use and configuration of the PS in a hardware design.
Software Design – Explores the software side of the Zynq device.
Debugging – Introduces debug tools and methodology on the Zynq SoC.
Tools and Reference Designs – Describes Xilinx-provided reference design platforms, use cases, and third-party operating systems and tools for the Zynq SoC.

Registration for this course is available through our Online Store.