Event

Designing FPGAs Using the VDS 1
August 25
- August 26
09:00 am
05:00 pm
Online
Register online in our secure store

This course offers introductory training on the Vivado Design Suite and helps you to understand the FPGA design flow.

After completing this comprehensive training, you will have the necessary skills to:

• Use the New Project Wizard to create a new Vivado IDE project
• Describe the supported design flows of the Vivado IDE
• Generate a DRC report to detect and fix design issues early in the flow
• Use the Vivado IDE I/O Planning layout to perform pin assignments
• Synthesis and implement the HDL Design
• Apply clock and I/O timing constraints and perform timing analysis
• Describe the "baselining" process to gain timing closure on a design
• Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
• Use the Vivado logic analyzer and debug flows to debug a design

Course Outline 2022.1

Day 1

• Intro to FPGA Architecture, 3D IC, SoC (Lecture)
• UltraFast Design Methodology: Board and Device Planning (Lecture, Demo)
• HDL Coding Techniques (Lecture)
• Introduction to the Vivado Design Flows (Lecture)
• Vivado Design Suite Project Mode (Lecture,Lab)
• Behavior Simulation (Lecture)
• Synthesis and Implementation (Lecture,Lab)
• Basic Design Analysis in the Vivado IDE (Lab, Demo)
• Vivado Design Rule Checks (Lab)
• Vivado Design Suite I/O Pin Planning (Lecture, Lab)
• Vivado IP Flow (Lecture, Lab, Demo)

Day 2

• Introduction to Clock Constraints  (Lecture,Lab, Demo)
• Generated Clocks (Lecture, Demo)
• I/O Constraints and Virtual Clocks (Lecture, Lab)
• Timing Constraints Wizard (Lecture, Lab)
• Introduction to Vivado Reports (Lecture, Demo)
• Setup and Hold Timing Analysis (Lecture)
• Xilinx Power Estimator Spreadsheet (Lecture, Lab)
• Introduction to FPGA Configuration (Lecture)
• Introduction to Vivado Logic Analyzer (Lecture,Lab)
• Introduction to Triggering (Lecture)
• Debug Cores (Lecture)
• Introduction to the Tcl Environment (Lecture,Lab)
• Using Tcl Commands in the Vivado Design Suite Project Flow (Lecture,Demo)
• Tcl Syntax and Structure (Lecture)

Topic Descriptions

Day 1

• Intro to FPGA Architecture, 3D IC, SoC-Overview of FPGA architecture, SSI technology, and SoC device architecture.
• UltraFast Design Methodology:Board and Device Planning - Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
• HDL Coding Techniques - Covers basic digital coding guidelines used in an FPGA Design.
• Introduction to the Vivado Design Flows- Introduces the Vivado design flows: the project flow and non-project batch flow.
• Vivado Design Suite Project Mode- Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
• BehaviorSimulation - Performs behaviorial simulation for your design.
• Synthesis and Implementation-Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
• Basic Design Analysis in the Vivado IDE - Use the various design analysis features in the Vivado Design Suite.
• Vivado Design Rule Checks- Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations.
• Vivado Design Suite I/O Pin Planning - Use the I/O Pin Planning layout to perform pin assignments in a design.
• Vivado IP Flow- Customize IP, instantiate IP, and verify the hierarchy of your design IP.

Day 2

• Introduction to Clock Constraints - Apply clock constraints and perform timing analysis.
• Generated Clocks - use the report clock networks report to determine if there are any generated clocks in a design.
• I/O Constraints and Virtual Clocks - Apply I/O constraints and perform timing analysis.
• Timing Constraints Wizard - Use the Timing Constraints Wizard to apply missing timing constraints in a design.

Register Today
 Registration for this course is available through our Online Store.