Course Calendar
BEGIN:VCALENDAR VERSION:2.0 PRODID:-//TYPO3/NONSGML Calendar Base (cal) V1.2.0//EN METHOD:PUBLISH BEGIN:VEVENT UID:_1_24 DTSTAMP:20090424T183434 DTSTART:20090527T150000Z DTEND:20090529T230000Z CATEGORIES:Languages SUMMARY:Introduction to VHDL DESCRIPTION:This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectureswith practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.\n\nIn this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nWrite RTL VHDL code for synthesisWrite VHDL testbenches for simulationCreate Finite State Machines (FSMs) by using VHDLTarget and optimize Xilinx FPGAs by using VHDLCreate RAM and ROM data structuresUse VHDL scalar and composite data typesRun a simulation by using VITAL librariesUse the VHDL textio package during simulationCreate and manage designs within the ISE software design environment \n\n Course OutlineDay 1\n\nCourse AgendaHardware Modeling OverviewVHDL Language ConceptsLab 1: Building HierarchyIntroduction to TestbenchesLab 2: VHDL Simulation and RTL VerificationSignals and Data TypesVHDL Operators and ExpressionsLab 3: Memory\n\nDay 2\n\nConcurrent and Sequential StatementsLab 4: Clock Divider and Address CounterControlled Operation StatementsLab 5: n-bit Binary Counter and RTL VerificationVITAL: VHDL Initiative toward ASIC LibrariesLab 6: Timing SimulationBehavioral to RTL Coding\n\nDay 3\n\nFinite State MachinesLab 7: Finite State MachinesTargeting Xilinx FPGAsLab 8: Implement and DownloadFunctions and ProceduresAdvanced Process StatementsLab 9: Text I/O\n\nLab Descriptions\n\nThe labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that you will verify in simulation.\n\nRegister Today\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_78 DTSTAMP:20090828T202054 DTSTART:20100113T160000Z DTEND:20100116T000000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. END:VEVENT BEGIN:VEVENT UID:_1_110 DTSTAMP:20100203T173735 DTSTART:20100330T150000Z DTEND:20100401T230000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing with VHDL" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_111 DTSTAMP:20100203T175547 DTSTART:20100413T150000Z DTEND:20100415T230000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing with VHDL" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_47 DTSTAMP:20090727T153642 DTSTART:20100420T150000Z DTEND:20100422T230000Z CATEGORIES:Languages SUMMARY:Designing with Verilog DESCRIPTION:This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.\n\nIn this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.After completing this comprehensive training, you will have the necessary skills to: \n\n Write RTL Verilog code for synthesisWrite Verilog test fixtures for simulationCreate a Finite State Machine (FSM) by using VerilogTarget and optimize Xilinx FPGAs by using VerilogUse enhanced Verilog file I/O capabilityRun a timing simulation by using Xilinx Simprim librariesCreate and manage designs within the ISE software design environmentDownload to the Spartan®-3E FPGA 1600E demo board \n\nCourse OutlineDay 1\n\n Hardware Modeling OverviewVerilog Language ConceptsModules and PortsLab 1: Building HierarchyIntroduction to TestbenchesLab 2: Verilog Simulation and RTL Verification \n\nDay 2\n\n Verilog Operators and ExpressionsData Flow-Level ModelingLab 3: MemoryVerilog Procedural StatementsLab 4: Clock Divider and Address CounterControlled Operation StatementsLab 5: n-bit Binary Counter and RTL Verification \n\nDay 3\n\nVerilog Tasks and FunctionsAdvanced Language ConceptsLab 6: Timing SimulationFinite State MachinesLab 7: Finite State MachinesTargeting Xilinx FPGAsLab 8: Implement and DownloadAdvanced Verilog TestbenchesLab 9: Using Verilog File I/O\n\nLab Descriptions The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation. \n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Salt Lake City, UT (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_60 DTSTAMP:20090727T210733 DTSTART:20100518T150000Z DTEND:20100520T230000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:\n\nThis comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. \n\nIn this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.\n\n\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nImplement the VHDL portion of coding for synthesisIdentify the differences between behavioral and structural coding stylesDistinguish coding for synthesis versus coding for simulationUse scalar and composite data types to represent informationUse concurrent and sequential control structure to regulate information flowImplement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)Simulate a basic VHDL designWrite a VHDL testbench and identify simulation-only constructsIdentify and implement coding best practicesOptimize VHDL code to target specific silicon resources within the Xilinx FPGACreate and manage designs within the ISE software environment\n\nCourse Outline\n\nDay 1\n\nThe “Shape” of VHDLLab 1: Using the ToolsDocumentation in VHDLData TypesConcurrent OperationsLab 2: Using Concurrent StatementsProcesses and VariablesLab 3: Designing a Simple Process\n\nDay 2\n\nIntroduction to TestbenchesISim Simulation Tool BasicsLab 4: Simulating a Simple DesignCreating MemoryLab 5: Building a Dual-Port MemoryFinite State MachinesLab 6: Building a Moore Finite State MachineTargeting Xilinx FPGAsLab 7: Xilinx Tool Flow\n\nDay 3\n\nLoops and Conditional ElaborationLab 8: Using LoopsAttributesFunctions and ProceduresPackages and LibrariesLab 9: Building Your Own PackageInteracting with the SimulationWriting a Good TestbenchLab 10: Building a Meaningful Testbench\n\nLab Descriptions\n\nThe labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Houston, TX (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_140 DTSTAMP:20100719T144701 DTSTART:20100816T150000Z DTEND:20100818T230000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing with VHDL" classes in our online store": END:VEVENT END:VCALENDARSee a list of all currently scheduled courses.
Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates. If there are no currently scheduled classes that are convenient, please tell us what dates and locations will meet your needs. No obligation necessary.
Student Cancellation Policy
Student cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
Student cancellations must be sent to registrar(at)fastertechnology.com
Faster Technology Course Cancellation Policy
Due to low class size and other certain considerations, Faster Technology may cancel a class up to 7 days before the scheduled start date of the class. In such cases, all students will be entitled to a 100% refund. Faster Technology will notify registered students of "at risk" classes prior to cancellation.
Under no circumstances is Faster Technology responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.