Course Calendar
BEGIN:VCALENDAR VERSION:2.0 PRODID:-//TYPO3/NONSGML Calendar Base (cal) V1.2.0//EN METHOD:PUBLISH BEGIN:VEVENT UID:_1_101 DTSTAMP:20091202T174715 DTSTART:20100202T160000Z DTEND:20100205T000000Z CATEGORIES:Connectivity SUMMARY:Signal Integrity and Board Design for Xilinx FPGAs DESCRIPTION:Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design technique and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe signal integrity effectsPredict and overcome signal integrity challenges Simulate signal integrity effectsVerify and derive design rules for the board designApply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and semiconductor circuitsPlan your board design under FPGA-specific restrictionsSupply the FPGAs with powerHandle thermal aspects\n\n Course OutlinePart 1 - Signal Integrity\n\nSignal Integrity IntroductionTransmission LinesIBIS Models and SI ToolsLab 1: Invoking HyperLynxReflectionsLab 2: Reflection AnalysisCrosstalkLab 3: Crosstalk AnalysisSignal Integrity AnalysisPower Supply IssuesSignal Integrity Summary\n\nPart 2 - Board Design\n\nBoard Design IntroductionFPGA Power SupplyLab 4: Power PredictionFPGA Configuration and PCBSignal Interfacing: Interfacing in GeneralSignal Interfacing: FPGA-Specific Interfacing Lab 5: I/O Pin PlanningDie Architecture and PackagingPCB DetailsThermal AspectsLab 6: Thermal DesignTools for PCB Planning and DesignBoard Design Summary\n\nLab Descriptions\n\nLab 1: Invoking HyperLynx – Get familiar with signal integrity tools. Use HyperLynx for schematic entry, modeling, and simulation. Modify a standard IBIS model to define a driver and then use its stackup editor to define a PCB.Lab 2: Reflection Analysis – Define a circuit and run various simulations for effects of reflection.Lab 3: Crosstalk Analysis – Using simulation, analyze circuit topology and PCB data for strategies to minimize crosstalk.Lab 4: Power Prediction – Estimate initial power requirements using an Excel spreadsheet, then use XPower Analyzer to accurately predict board power needs.Lab 5: I/O Pin Planning – Use the ISE tools or PlanAhead software to identify pin placement and implement pin assignments.Lab 6: Thermal Design – Determine maximum junction temperature and calculate acceptable thermal resistance.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Courtyard Salt Lake City Airport (4843 West Douglas Corrigan Way, Salt Lake City, Utah 84116) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_57 DTSTAMP:20090727T204619 DTSTART:20100303T160000Z DTEND:20100306T000000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT FPGA or Virtex®-6 LXT or SXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGAEffectively utilize the following features of the GTP/GTX:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalizationUse the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a designAccess appropriate reference material for board design issues involving the power supply, reference clocking, and trace design\n\nCourse Outline\n\nDay 1\n\nCourse Agenda and IntroductionSpartan-6 and Virtex-6 Family OverviewTransceiver OverviewTransceiver Clocking and Resets8B/10B Encoder and Decoder Lab 1: 8B/10B Disparity and BypassCommas and Deserializer Alignment Lab 2: Commas and Data Alignment\n\nDay 2\n\nRX Elastic Buffer and Clock CorrectionLab 3: Clock CorrectionChannel Bonding Lab 4: Channel BondingGTP Wizard OverviewLab 5: GTP Core GenerationTransceiver Implementation and SimulationLab 6: Implementation and SimulationPhysical Media Attachments\n\nDay 3\n\nVirtex-6 FPGA 64B/66B Encoding and the GearboxLab 7: GTX 64B/66B EncodingTransceiver Board Design RocketIO Transceiver Test and DebuggingLab 8: System LabRocketIO Transceiver Application Examples\n\nLab Descriptions\n\nLab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.Lab 5: GTP Core Generation – Use the GTP Wizard to create instantiation templates.Lab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design. Lab 7: GTX 64B/66B Encoding – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results.Lab 8: System Lab – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.\n\n\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_118 DTSTAMP:20100506T171004 DTSTART:20100526T150000Z DTEND:20100527T230000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGAEffectively utilize the following features of the GTP/GTX:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalizationUse the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a designAccess appropriate reference material for board design issues involving the power supply, reference clocking, and trace design\n\nCourse Outline\n\nSpartan-6 and Virtex-6 Family OverviewTransceiver Overview (GTP, GTX, GTH)Transceiver Clocking and Resets8B/10B Encoder and Decoder Lab 1: 8B/10B Disparity and BypassCommas and Deserializer Alignment Lab 2: Commas and Data AlignmentRX Elastic Buffer and Clock CorrectionLab 3: Clock CorrectionChannel Bonding Lab 4: Channel BondingTransceiver Wizard OverviewLab 5: GTP WizardImplementing and Simulating a Transceiver DesignLab 6: Implementation and SimulationPhysical Media Attachments64B/66B Encoding and the GearboxLab 7: 64B/66B GTX TransceiverTransceiver-Specific Board Design ConsiderationsRocketIO Transceiver Test and DebuggingLab 8: System LabRocketIO Transceiver Application Examples\n\nLab Descriptions\n\nLab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.Lab 5: GTP Wizard – Use the GTP Wizard to create instantiation templatesLab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design. Lab 7: 64B/66B GTX Transceiver – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results. Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Avnet Electronics Marketing (9601 Amberglen Blvd. Suite 250, Austin, TX 78729) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_138 DTSTAMP:20100611T154211 DTSTART:20100621T150000Z DTEND:20100622T230000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing with Multi-Gigabit Serial I/O" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_146 DTSTAMP:20100802T192639 DTSTART:20100913T150000Z DTEND:20100915T230000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGAEffectively utilize the following features of the GTP/GTX:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalizationUse the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a designAccess appropriate reference material for board design issues involving the power supply, reference clocking, and trace design\n\nCourse Outline\n\nSpartan-6 and Virtex-6 Family OverviewTransceiver Overview (GTP, GTX, GTH)Transceiver Clocking and Resets8B/10B Encoder and Decoder Lab 1: 8B/10B Disparity and BypassCommas and Deserializer Alignment Lab 2: Commas and Data AlignmentRX Elastic Buffer and Clock CorrectionLab 3: Clock CorrectionChannel Bonding Lab 4: Channel BondingTransceiver Wizard OverviewLab 5: GTP WizardImplementing and Simulating a Transceiver DesignLab 6: Implementation and SimulationPhysical Media Attachments64B/66B Encoding and the GearboxLab 7: 64B/66B GTX TransceiverTransceiver-Specific Board Design ConsiderationsRocketIO Transceiver Test and DebuggingLab 8: System LabRocketIO Transceiver Application Examples\n\nLab Descriptions\n\nLab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.Lab 5: GTP Wizard – Use the GTP Wizard to create instantiation templatesLab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design. Lab 7: 64B/66B GTX Transceiver – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results. Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_151 DTSTAMP:20100802T194422 DTSTART:20101013T150000Z DTEND:20101015T230000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGAEffectively utilize the following features of the GTP/GTX:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalizationUse the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a designAccess appropriate reference material for board design issues involving the power supply, reference clocking, and trace design\n\nCourse Outline\n\nSpartan-6 and Virtex-6 Family OverviewTransceiver Overview (GTP, GTX, GTH)Transceiver Clocking and Resets8B/10B Encoder and Decoder Lab 1: 8B/10B Disparity and BypassCommas and Deserializer Alignment Lab 2: Commas and Data AlignmentRX Elastic Buffer and Clock CorrectionLab 3: Clock CorrectionChannel Bonding Lab 4: Channel BondingTransceiver Wizard OverviewLab 5: GTP WizardImplementing and Simulating a Transceiver DesignLab 6: Implementation and SimulationPhysical Media Attachments64B/66B Encoding and the GearboxLab 7: 64B/66B GTX TransceiverTransceiver-Specific Board Design ConsiderationsRocketIO Transceiver Test and DebuggingLab 8: System LabRocketIO Transceiver Application Examples\n\nLab Descriptions\n\nLab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.Lab 5: GTP Wizard – Use the GTP Wizard to create instantiation templatesLab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design. Lab 7: 64B/66B GTX Transceiver – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results. Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_137 DTSTAMP:20100601T203954 DTSTART:20101025T150000Z DTEND:20101026T230000Z CATEGORIES:Connectivity SUMMARY:Designing a LogiCORE PCI Express System DESCRIPTION:Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system with supporting logic and example designs. With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the Spartan®-6 FPGA PCIe Integrated Endpoint block.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nConstruct a basic PCIe system by:Selecting the appropriate core for your applicationSpecifying requirements of an endpoint applicationConnecting this endpoint with the coreUtilizing FPGA resources to support the coreSimulating the designIdentify the advanced capabilities of the PCIe specification protocol and feature set\n\nCourse Outline\n\nDay 1\n\nCourse Introduction Introduction to the PCIe ArchitectureReview of the PCIe ProtocolPCIe and the CORE Generator™ ToolLab 1: Constructing the PCIe CoreSimulating a PCIe System DesignConnecting Logic to the Core – Local Link Memory Read and Memory Write Completion Details Lab 2: Downstream Port Model Simulation Endpoint Application Considerations Lab 3: Pseudo-Transactional Modeling\n\nDay 2\n\nApplication Focus: DMA Lab 4: Design Implementation Virtex-6 FPGA Root Port Compliance and Debugging Lab 5: Debugging the PCIe Core with the ChipScope Pro Tools Errors and Interrupts Course Summary Appendix: Mechanicals, Hot Plug, and Power\n\nLab Descriptions\n\nLab 1: Constructing the PCIe Core – This lab familiarizes you with all the necessary flow of the Xilinx CORE Generator™ tool for generating a Xilinx LogiCORE Endpoint Block IP. You will select appropriate parameters for the CORE Generator tool and create the PCIe core used throughout the labs.Lab 2: Downstream Port Model Simulation – This lab demonstrates how timing and behavior of a typical link negotiation using the ISim tool. You will observe and capture the effects of link training and write packets to the endpoint application for later use.Lab 3: Pseudo-Transactional Modeling – This lab illustrates pseudo-transactional modeling, which provides various packets to the user design without the need to simulate the PCIe cores themselves.Lab 4: Design Implementation – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream. Lab 5: Debugging the PCIe Core with the ChipScope Pro Tools – This lab illustrates how to use the ChipScope™ Pro tools to monitor the behavior of the core and the endpoint application for proper operation.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT END:VCALENDARSee a list of all currently scheduled courses.
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Student Cancellation Policy
Student cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
Student cancellations must be sent to registrar(at)fastertechnology.com
Faster Technology Course Cancellation Policy
Due to low class size and other certain considerations, Faster Technology may cancel a class up to 7 days before the scheduled start date of the class. In such cases, all students will be entitled to a 100% refund. Faster Technology will notify registered students of "at risk" classes prior to cancellation.
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