Course Calendar
BEGIN:VCALENDAR VERSION:2.0 PRODID:-//TYPO3/NONSGML Calendar Base (cal) V1.2.0//EN METHOD:PUBLISH BEGIN:VEVENT UID:_1_70 DTSTAMP:20090828T150247 DTSTART:20091105T160000Z DTEND:20091107T000000Z CATEGORIES:DSP Design SUMMARY:DSP Design Using System Generator DESCRIPTION:This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nDescribe the System Generator design flow for implementing DSP functionsIdentify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulationList various low-level and high-level functional blocks available in System GeneratorIdentify the high-level blocks available for FIR and FFT designsDesign a multiple-clock-based System Generator systemEmbed two System Generator designs into a larger design\n\nCourse OutlineDay 1\n\nIntroduction to System GeneratorSimulink Software BasicsLab 1: Using the Simulink SoftwareBasic Xilinx Design CaptureLab 2: Getting Started with Xilinx System GeneratorSignal RoutingLab 3: Signal RoutingImplementing System ControlLab 4: Implementing System Control\n\nDay 2\n\nMulti-Rate SystemsLab 5: Designing a MAC-Based FIR Filter DesignLab 6: Designing a FIR Filter Using the FIR Compiler Block Xilinx System Generator, Project Navigator, and Platform Studio IntegrationLab 7: System Generator and Project Navigator IntegrationLab 8: System Generator, Project Navigator, and Platform Studio Integration\n\nLab Descriptions\n\nLab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based (ML505 board) design. Perform hardware co-simulation verification targeting an ML505 board.Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using an ML505 board.Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using the ML505 board.Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.Lab 8: System Generator, Project Navigator, and Platform Studio Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_102 DTSTAMP:20091202T185105 DTSTART:20100311T160000Z DTEND:20100313T000000Z CATEGORIES:DSP Design SUMMARY:DSP Design Using System Generator DESCRIPTION:This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the System Generator design flow for implementing DSP functionsIdentify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulationList various low-level and high-level functional blocks available in System GeneratorIdentify the high-level blocks available for FIR and FFT designsDesign a multiple-clock-based System Generator systemEmbed two System Generator designs into a larger designUse a custom-designed FPGA PCB as a hardware co-simulation target\n\nCourse Outline\n\nDay 1\n\nIntroduction to System GeneratorSimulink Software BasicsLab 1: Using the Simulink SoftwareBasic Xilinx Design CaptureLab 2: Getting Started with Xilinx System GeneratorSignal RoutingLab 3: Signal RoutingImplementing System ControlLab 4: Implementing System Control\n\nDay 2\n\nMulti-Rate SystemsLab 5: Designing a MAC-Based FIR Filter DesignLab 6: Designing a FIR Filter Using the FIR Compiler Block Xilinx System Generator, Project Navigator, and Platform Studio IntegrationLab 7: System Generator and Project Navigator Integration\n\nLab Descriptions\n\nLab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_115 DTSTAMP:20100317T123955 DTSTART:20100930T150000Z DTEND:20101001T230000Z CATEGORIES:DSP Design SUMMARY:DSP Design Using System Generator DESCRIPTION:This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the System Generator design flow for implementing DSP functionsIdentify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulationList various low-level and high-level functional blocks available in System GeneratorUse custom boards for hardware co-simulationIdentify the high-level blocks available for FIR and FFT designsDesign a multiple-clock-based System Generator systemEmbed two System Generator designs into a larger design\n\nCourse Outline\n\nDay 1\n\nIntroduction to System GeneratorSimulink Software BasicsLab 1: Using the Simulink SoftwareBasic Xilinx Design CaptureLab 2: Getting Started with Xilinx System GeneratorSignal RoutingLab 3: Signal RoutingImplementing System ControlLab 4: Implementing System Control\n\nDay 2\n\nMulti-Rate SystemsLab 5: Designing a MAC-Based FIR Filter DesignLab 6: Designing a FIR Filter Using the FIR Compiler Block System Generator, Project Navigator, and Platform Studio IntegrationLab 7: System Generator and Project Navigator IntegrationSpartan-6 and Virtex-6 FPGA DSP PlatformsLab 8: Using System Generator to Develop Virtex-6 and Spartan-6 FPGA DSP Applications\n\nLab Descriptions\n\nLab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.Lab 8: Using System Generator to Develop Virtex-6 and Spartan-6 FPGA DSP Applications – Design a single-carrier Digital Up Converter (DUC) and Digital Down Converter (DDC) to meet WCDMA UTMS 3GPP specifications.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT END:VCALENDARSee a list of all currently scheduled courses.
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