Course Calendar
BEGIN:VCALENDAR VERSION:2.0 PRODID:-//TYPO3/NONSGML Calendar Base (cal) V1.2.0//EN METHOD:PUBLISH BEGIN:VEVENT UID:_1_46 DTSTAMP:20090727T153131 DTSTART:20090810T150000Z DTEND:20090811T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Registration for this course is available through our Online Store.\n\nXilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the EDK environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse OutlineDay 1\n\n EDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading SoftwareSystem BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\n Interfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building a Custom IP Peripheral for an Embedded System – PLB v46 BusBus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions Both the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the Virtex®-5 FPGA ML507 and Spartan®-3E FPGA boards.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design.Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the board.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building a Custom IP Peripheral for an Embedded System – Create and add custom IP (IPIC interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in the design.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_92 DTSTAMP:20090915T150024 DTSTART:20091020T150000Z DTEND:20091021T230000Z CATEGORIES:Embedded Design SUMMARY:Advanced Embedded Systems Development DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site END:VEVENT BEGIN:VEVENT UID:_1_96 DTSTAMP:20091001T163658 DTSTART:20091116T160000Z DTEND:20091118T000000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the EDK environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse OutlineDay 1\n\n EDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading SoftwareSystem BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\n Interfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building a Custom IP Peripheral for an Embedded System – PLB v46 BusBus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions Both the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the Virtex®-5 FPGA ML507 and Spartan®-3E FPGA boards.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design.Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the board.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building a Custom IP Peripheral for an Embedded System – Create and add custom IP (IPIC interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in the design.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_72 DTSTAMP:20090828T162232 DTSTART:20091118T160000Z DTEND:20091120T000000Z CATEGORIES:Embedded Design SUMMARY:Advanced Embedded Systems Development DESCRIPTION:Advanced Features and Techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system. This course builds on the skills gained in the Embedded Systems Development course. Labs provide hands-on experience with the development, verification, debugging, and simulation of an embedded system. Some labs use the Virtex®-5 FPGA ML507 demo board in which designs are downloaded and verified.After completing this comprehensive training, you will have the necessary skills to: \n\nAssemble an advanced embedded systemTake advantage of the various Virtex-5 FPGA and PowerPC® 440 processor features, including the crossbar and multi-port memory controllerApply advanced debugging techniques, including the use of the ChipScope™ tool for debugging an embedded system and HDL system simulationIdentify the steps involved in integrating a memory controller into an embedded system using the PowerPC 440 processorIntegrate an interrupt controller and interrupt handler into your embedded designDesign a Flash memory-based system and boot load from off-chip Flash memory Perform HDL-based system simulation\n\nCourse OutlineDay 1\n\nEmbedded Systems Development ReviewLab 1: Building a Complete Embedded SystemPowerPC 440 Processor CrossbarDebugging Using the ChipScope Pro AnalyzerLab 2: Debugging Using the ChipScope Pro AnalyzerBlock RAM Memory ControllersMulti-Channel External Memory Controller for Static MemoryPowerPC 440 Processor DDR2 Memory Controller for the Crossbar MCIMulti-Port Memory Controller for Dynamic RAMLab 3: Instantiating a DDR2 Memory Controller\n\nDay 2\n\nInterruptsFast Simplex LinksAdvanced Processor and Peripheral Interface OptionsLab 4: Interfacing an Embedded System to FPGA FabricAdvanced Processor ConfigurationsBoot LoaderLab 5: Boot Loading from Flash MemoryHDL System Simulation in XPSLab 6: Simulating an Embedded Processor System\n\nLab Descriptions \n\nLab 1: Building a Complete Embedded System – Develop hardware that incorporates IP cores to interface to push buttons, switches, LEDs, an LCD display, and serial communication. Develop an application that interacts with switches, push buttons, an LCD display, and serial communication. Generate and download a bitstream onto the ML507 demo board.Lab 2: Debugging Using the ChipScope Pro Analyzer – Perform simultaneous hardware and software debugging with the ChipScope™ Pro Analyzer, SDK Debug perspective, and XMD.Lab 3: Instantiating a DDR2 Memory Controller – Use XPS to instantiate a DDR2 memory controller. Explore memory device parameter configurations and proper memory controller clocking procedures.Lab 4: Interfacing an Embedded System to FPGA Fabric – Move data between an embedded system and FPGA fabric via an FSL and a dual-port block RAM. Implement an interrupt controller and an interrupt handler.Lab 5: Boot Loading from Flash Memory – Develop an application that is stored in flash memory, load it through a boot loader program, and execute the software from external memory. Lab 6: Simulating an Embedded Processor System – Set up and perform HDL-based simulation on an embedded processor system. Explore the tool flow for performing embedded processor simulation as part of a Project Navigator design in the ISE software.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_100 DTSTAMP:20091103T180018 DTSTART:20100120T160000Z DTEND:20100122T000000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the EDK environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse OutlineDay 1\n\n EDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading SoftwareSystem BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\n Interfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building a Custom IP Peripheral for an Embedded System – PLB v46 BusBus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions Both the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the Virtex®-5 FPGA ML507 and Spartan®-3E FPGA boards.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design.Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the board.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building a Custom IP Peripheral for an Embedded System – Create and add custom IP (IPIC interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in the design.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_83 DTSTAMP:20090828T203122 DTSTART:20100325T150000Z DTEND:20100326T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.\n\n* This course focuses on the Virtex-5, Virtex-6, and Spartan-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the EDK environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse Outline\n\nDay 1\n\nEDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading Software System BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\nInterfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building a Custom IP Peripheral for an Embedded System – PLB v46 Bus Bus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions\n\nBoth the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the Spartan-6 FPGA SP605, Spartan-3E FPGA 1600E, or Virtex-5 FPGA ML507 boards.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design. Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the board.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building a Custom IP Peripheral for an Embedded System – Create and add custom IP (IPIC interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in the design.\n\n\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_112 DTSTAMP:20100322T164716 DTSTART:20100428T150000Z DTEND:20100429T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Software Development DESCRIPTION:This two-day course introduces you to software design and development for Xilinx embedded processor systems. You will learn the basic tool use and concepts required for the software phase of the design cycle, after the hardware design is completed.\n\nTopics are comprehensive, covering the design and implementation of the software platform for resource access and management. Major topics include device driver development and user application debugging and integration. Practical implementation tips and best practices are also provided throughout to enable you to make good design decisions and keep your design cycles to a minimum. You will have enough practical information to get started developing the software platform for a Xilinx embedded system based on a PowerPC® 440 or MicroBlaze™ processor. \n\nWhile this course includes many of the topics presented in the Embedded Systems Development and Advanced Features and Techniques of Embedded Systems Development courses, the focus is on software development concepts and practices rather than hardware development. Hardware design concepts and procedures are not covered.* This course focuses on the Virtex-5 architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nImplement an effective software design environment for a Xilinx embedded system using the Xilinx SDK toolsWrite a basic user application using the Xilinx Software Development Kit (SDK) and run it on the embedded system Use Xilinx debugger tools to troubleshoot user applicationsApply software techniques to improve operabilityReduce embedded software development time\n\nCourse Outline\n\nDay 1\n\nCourse AgendaProcessors, Peripherals, and ToolsSoftware Platform DevelopmentLab 1: Basic System ImplementationWriting Code in the Xilinx EnvironmentSoftware Development Using SDKLab 2: Application DevelopmentAddress ManagementInterruptsLab 3: Software Interrupts\n\nDay 2\n\nSoftware Platform Download and BootApplication DebuggingLab 4: DebuggingApplication ProfilingLab 5: SDK ProfilingWriting a Custom Device DriverLab 6: Writing a Device DriverAdvanced Services and Operating SystemsProject Management with the Xilinx Design ToolsLab 7: File Systems\n\nLab Descriptions\n\nLab 1: Basic System Implementation – Construct the hardware and software platforms used for the labs. Begin with Base System Builder to create the hardware design. Specify a basic software platform and add a software application to the system.Lab 2: Application Development – Create a simple software application project from source files for a software loop-based stopwatch. Research hardware and software documentation to complete the application; then download it to hardware.Lab 3: Software Interrupts – Replace a software timing loop with an interrupt-driven timer. Add the timer software and write an interrupt handler for the timer. Configure the FPGA, download, and test the application.Lab 4: Debugging – Set up the SDK debug perspective and the previous lab’s stopwatch application for debugging, setting breakpoints, calculating interrupt latency, and stepping through the program’s operation.Lab 5: SDK Profiling – Profile a program, interpret reports, then enable cache and rewrite code to archive optimal performance.Lab 6: Writing a Device Driver – Create the skeleton driver framework, add an LCD device driver to the BSP, and verify proper device driver operation via a download to hardware test.Lab 7: External Memory Controllers and File Systems – Implement a standalone software platform that incorporates the XilMFS memory file system. Develop an application that performs file-related tasks on external memory.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_147 DTSTAMP:20100802T193028 DTSTART:20101018T150000Z DTEND:20101019T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.\n\n* This course focuses on the Spartan-6, Virtex-5, and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the Project Navigator environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse Outline\n\nDay 1\n\nEDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading Software System BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\nInterfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building Custom IP for an Embedded System – PLB v46 Bus Bus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions\n\nBoth the MicroBlaze and PowerPC 440 processors are supported in the labs.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design. Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 using the SDK tools to create a software BSP and sample application. Configure the FPGA and download the application.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building Custom IP for an Embedded System – Create and add a custom PLB bus peripheral (LCD interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in an ISE design project.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_153 DTSTAMP:20100802T195227 DTSTART:20101021T150000Z DTEND:20101022T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.\n\n* This course focuses on the Spartan-6, Virtex-5, and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the Project Navigator environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse Outline\n\nDay 1\n\nEDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading Software System BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\nInterfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building Custom IP for an Embedded System – PLB v46 Bus Bus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions\n\nBoth the MicroBlaze and PowerPC 440 processors are supported in the labs.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design. Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 using the SDK tools to create a software BSP and sample application. Configure the FPGA and download the application.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building Custom IP for an Embedded System – Create and add a custom PLB bus peripheral (LCD interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in an ISE design project.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Salt Lake City, UT (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_154 DTSTAMP:20100802T195451 DTSTART:20101027T150000Z DTEND:20101028T230000Z CATEGORIES:Embedded Design SUMMARY:Advanced Embedded Systems Development DESCRIPTION:Advanced Features and Techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system. This course builds on the skills gained in the Embedded Systems Development course. Labs provide hands-on experience with the development, verification, debugging, and simulation of an embedded system. Labs use the Spartan®-6 FPGA SP605 or Virtex®-5 FPGA ML507 demo boards in which designs are downloaded and verified.\n\n* This course focuses on the Spartan-6, Virtex-5, and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nAssemble an advanced embedded systemTake advantage of the various Virtex and Spartan FPGA and PowerPC 440 and MicroBlaze processor features, including the crossbar and multi-port memory controllerApply advanced debugging techniques, including the use of the ChipScope™ tool for debugging an embedded system and HDL system simulation of processor-based designsIdentify the steps involved in integrating a memory controller into an embedded system using the PowerPC 440 and the MicroBlaze processorsIntegrate an interrupt controller and interrupt handler into your embedded designDesign a Flash memory-based system and boot load from off-chip Flash memory Perform HDL-based system simulation\n\nCourse Outline\n\nDay 1\n\nEmbedded Systems Development ReviewLab 1: Building a Complete Embedded SystemPowerPC 440 Processor CrossbarDebugging Using the ChipScope Pro AnalyzerLab 2: Debugging Using the ChipScope Pro AnalyzerBlock RAM Memory ControllersMulti-Channel External Memory Controller for Static MemoryPowerPC 440 Processor DDR2 Memory Controller for the Crossbar MCIMulti-Port Memory Controller for Dynamic RAMLab 3: Instantiating a DDR Memory Controller\n\nDay 2\n\nInterruptsFast Simplex LinksAdvanced Processor and Peripheral Interface OptionsLab 4: Interfacing an Embedded System to FPGA FabricAdvanced Processor ConfigurationsBoot LoaderLab 5: Boot Loading from Flash MemoryHDL System Simulation in XPSLab 6: Simulating an Embedded Processor System\n\nLab Descriptions\n\nLab 1: Building a Complete Embedded System – Develop hardware that incorporates IP cores to interface to push buttons, a rotary switch, LEDs, an LCD display, and serial communication. Use the SDK development tools to create an embedded software application project for the hardware built. Lab 2: Debugging Using the ChipScope Pro Analyzer – Perform simultaneous hardware and software debugging with the ChipScope™ Pro Analyzer, SDK Debug perspective, and XMD.Lab 3: Instantiating a DDR Memory Controller – Use XPS to instantiate a DDR memory controller. Explore memory device configurations and proper memory controller clocking procedures.Lab 4: Interfacing an Embedded System to FPGA Fabric – Move data between an embedded system and FPGA fabric via an FSL and a dual-port block RAM. Implement an interrupt controller and an interrupt handler.Lab 5: Boot Loading from Flash Memory – Develop an application that is stored in flash memory, load it through a boot loader program, and execute the software from external memory. Lab 6: Simulating an Embedded Processor System – Set up and perform HDL-based simulation on a design that contains an embedded processor system. Explore the tool flow for performing embedded processor simulation as part of a Project Navigator design in the ISE software.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT END:VCALENDARSee a list of all currently scheduled courses.
Faster Technology is able to deliver both private classes at client sites and also public classes at alternate locations and dates. If there are no currently scheduled classes that are convenient, please tell us what dates and locations will meet your needs. No obligation necessary.
Student Cancellation Policy
Student cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
Student cancellations must be sent to registrar(at)fastertechnology.com
Faster Technology Course Cancellation Policy
Due to low class size and other certain considerations, Faster Technology may cancel a class up to 7 days before the scheduled start date of the class. In such cases, all students will be entitled to a 100% refund. Faster Technology will notify registered students of "at risk" classes prior to cancellation.
Under no circumstances is Faster Technology responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.