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Course Calendar

BEGIN:VCALENDAR VERSION:2.0 PRODID:-//TYPO3/NONSGML Calendar Base (cal) V1.2.0//EN METHOD:PUBLISH BEGIN:VEVENT UID:_1_17 DTSTAMP:20090330T193955 DTSTART:20090429T150000Z DTEND:20090429T230000Z CATEGORIES:FPGA Design SUMMARY:Fundamentals of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE 10.1 features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.Note that one of the prerequisites of Fundamentals of FPGA Design is the completion of the basic FPGA architecture modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to:\n\nUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Architecture Wizard to create DCM instantiationsUse the Floorplan Editor and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraintsLocate and modify the implementation options\n\nCourse Outline\n\nCourse AgendaXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Architecture Wizard and Floorplan Editor/PACE Lab 3: Pre-Assigning I/O Pins Using PinAhead Global Timing ConstraintsLab 4: Global Timing Constraints Implementation OptionsLab 5: Implementation Options Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the Architecture Wizard and the Floorplan Editor or PACE in the design process. Implement a design by using default software options. The design will be simulated and downloaded to a Spartan®-3E FPGA 1600 demo board.Lab 2: Architecture Wizard and Floorplan Editor/PACE – Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design.Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.Lab 5: Implementation Options – Adjust process properties and I/O configuration options to improve the design performance.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_13 DTSTAMP:20090401T160642 DTSTART:20090430T150000Z DTEND:20090501T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.Note that one of the prerequisites of Designing for Performance is the completion of the HDL coding style modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Fundamentals of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformancePower Estimation (Optional)Lab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources.Lab 3: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:(TBD) Dallas, TX END:VEVENT BEGIN:VEVENT UID:_1_25 DTSTAMP:20090427T152756 DTSTART:20090601T150000Z DTEND:20090601T230000Z CATEGORIES:FPGA Design SUMMARY:Fundamentals of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE 10.1 features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.Note that one of the prerequisites of Fundamentals of FPGA Design is the completion of the basic FPGA architecture modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to:\n\nUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Architecture Wizard to create DCM instantiationsUse the Floorplan Editor and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraintsLocate and modify the implementation options\n\nCourse Outline\n\nCourse AgendaXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Architecture Wizard and Floorplan Editor/PACE Lab 3: Pre-Assigning I/O Pins Using PinAhead Global Timing ConstraintsLab 4: Global Timing Constraints Implementation OptionsLab 5: Implementation Options Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the Architecture Wizard and the Floorplan Editor or PACE in the design process. Implement a design by using default software options. The design will be simulated and downloaded to a Spartan®-3E FPGA 1600 demo board.Lab 2: Architecture Wizard and Floorplan Editor/PACE – Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design.Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.Lab 5: Implementation Options – Adjust process properties and I/O configuration options to improve the design performance.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_27 DTSTAMP:20090427T153208 DTSTART:20090602T150000Z DTEND:20090603T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.Note that one of the prerequisites of Designing for Performance is the completion of the HDL coding style modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Fundamentals of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformancePower Estimation (Optional)Lab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources.Lab 3: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_29 DTSTAMP:20090427T153425 DTSTART:20090604T150000Z DTEND:20090605T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 10.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 10.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.After completing this comprehensive training, you will have the necessary skills to: \n\nImplement designs via the Tcl command lineCreate and edit timing constraints in the UCF fileIdentify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesPreserve design results by using SmartGuide™ technology or partitionsUse the Floorplan Editor or Pinout and Area Constraints Editor (PACE) to create area constraintsChange signals of interest in the ChipScope™ Pro tool for boardlevel debugging using the FPGA Editor\n\nCourse Outline\n\n IntroductionLab 1: Achieving Timing Closure and Review of Global Timing ConstraintsTcl ScriptingLab 2: Tcl ScriptingUCF EditingLab 3: UCF EditingAdvanced I/O TimingLab 4: Advanced I/O TimingSmartCompile™ Technology Design Preservation TechniquesLab 5: SmartCompile TechnologyFloorplanning an Effective LayoutLab 6: FloorplanningFPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor\n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 10.1 software. \n\n Lab 1: Achieving Timing Closure and Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 2: Tcl Scripting – Write ISE tool control commands in a Tcl script file to implement the design. Then modify program switches to obtain the greatest possible performance from the design.Lab 3: UCF – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 4: Advanced I/O Timing – Compose timing constraints for an I/O interface. Analyze the timing failures and determine changes to correct the timing issues. Modify the design to fix timing failures.Lab 5: SmartCompile Technology – Utilize SmartGuide technology and partitions to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to enhance the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:BP Sales - Corporate Headquarters (2201 N Central Expy, Suite 255, Richardson, TX 75080) END:VEVENT BEGIN:VEVENT UID:_1_34 DTSTAMP:20090615T172412 DTSTART:20090713T150000Z DTEND:20090713T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:\n\nUse the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.\n\n \n\nThis course covers ISE software 11.1 features, such as the Architecture Wizard, PlanAhead™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. \n\n \n\nFor more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.Use\n\nthe ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE 10.1 features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.Note that one of the prerequisites of Fundamentals of FPGA Design is the completion of the basic FPGA architecture modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to:\n\nUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Architecture Wizard to create DCM instantiationsUse the Floorplan Editor and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraintsLocate and modify the implementation options\n\nCourse Outline\n\nCourse AgendaXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Architecture Wizard and Floorplan Editor/PACE Lab 3: Pre-Assigning I/O Pins Using PinAhead Global Timing ConstraintsLab 4: Global Timing Constraints Implementation OptionsLab 5: Implementation Options Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the Architecture Wizard and the Floorplan Editor or PACE in the design process. Implement a design by using default software options. The design will be simulated and downloaded to a Spartan®-3E FPGA 1600 demo board.Lab 2: Architecture Wizard and Floorplan Editor/PACE – Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design.Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.Lab 5: Implementation Options – Adjust process properties and I/O configuration options to improve the design performance.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_35 DTSTAMP:20090615T174332 DTSTART:20090714T150000Z DTEND:20090715T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Essentials of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformanceLab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate it into VHDL or Verilog source code, and implement the design.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement the design.Lab 3: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Versions of this lab are available for Xilinx XST and Synplify Pro software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_55 DTSTAMP:20090727T203627 DTSTART:20090916T150000Z DTEND:20090916T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.\n\nThis course covers ISE software 11.1 features, such as the Architecture Wizard, PlanAhead™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. \n\nFor more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Virtex®-5 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Architecture Wizard to create DCM instantiationsUse the PlanAhead tool and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Architecture Wizard Lab 3: Pre-Assigning I/O Pins Using PinAhead Global Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan®-3E FPGA 1600 demo board. Lab 2: Architecture Wizard and PlanAhead Tool – Use the Architecture Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_56 DTSTAMP:20090727T203921 DTSTART:20090917T150000Z DTEND:20090918T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Essentials of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformanceLab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate it into VHDL or Verilog source code, and implement the design.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement the design.Lab 3: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Versions of this lab are available for Xilinx XST and Synplify Pro software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_61 DTSTAMP:20090727T211023 DTSTART:20091028T150000Z DTEND:20091028T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 11.3 features, such as the Architecture Wizard, PlanAhead™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan®-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the PlanAhead tool and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan®-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and PlanAhead Tool – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_62 DTSTAMP:20090727T211128 DTSTART:20091029T150000Z DTEND:20091030T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Essentials of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformanceLab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate it into VHDL or Verilog source code, and implement the design.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement the design.Lab 3: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Versions of this lab are available for Xilinx XST and Synplify Pro software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_63 DTSTAMP:20090810T171415 DTSTART:20091109T160000Z DTEND:20091111T000000Z CATEGORIES:FPGA Design SUMMARY:Designing with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.\n\nNote: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.After completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun the Design Rule Checker (DRC) and WASSO analysisImport HDL sources, elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placementInsert ChipScope™ Pro tool debug coresFloorplan the design to improve performance and consistencyUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse OutlineDay 1\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsRTL Development and AnalysisLab 3: RTL Development and AnalysisImplementing a Design Lab 4: Implementing with the PlanAhead Tool\n\nDay 2\n\nDesign AnalysisLab 5: Design AnalysisFloorplanning TechniquesLab 6: FloorplanningDebugging with the ChipScope ToolLab 7: Debugging with the ChipScope ToolProject Navigator Integration with the PlanAhead ToolLab 8: Using the PlanAhead Tool with Project NavigatorCourse Summary\n\nLab DescriptionsNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope™ Pro cores and tools. Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAhead tool integrated within the ISE software Project Navigator environment.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_64 DTSTAMP:20090811T151921 DTSTART:20091111T160000Z DTEND:20091113T000000Z CATEGORIES:FPGA Design SUMMARY:Debugging Techniques Using the ChipScope Pro Tools DESCRIPTION:As FPGA designs become increasingly more complex, designers are looking to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for debug and verification. This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nMaximize ChipScope Pro tool core performanceMinimize negative timing impacts on a designEffectively utilize the various sampling coresVisualize captured data in the most advantageous fashionUse techniques that enhance and extend the capabilities of the ChipScope Pro toolsExecute remote debugging\n\nCourse OutlineDay 1 \n\nAgenda and IntroductionHow the ChipScope Pro Tool WorksInserting the Core Using Core Inserter and the PlanAhead SoftwareLab 1: Using the PlanAhead Tool and Core Inserter FlowsInstantiating the CoresLab 2: Using the Core Generator Flow Triggering Methods and Maximizing StorageVisualizing the Sampled Data Lab 3: Using the Analyzer ToolDay 1 Summary\n\nDay 2\n\nDay 2 IntroductionTips and TricksLab 4: Tips and TricksTime for TimingVideo Demo: Area Groups and the ChipScope Pro ToolCase StudiesLab 5: Data Collection and StorageScripting (Optional)*Lab 6: Scripting (Optional)*Remote Access (Optional)*Lab 7: Remote Access (Optional)*Summary\n\n\n\n* Please check with your ATP to confirm whether this content is included with your specific class.\n\nLab Descriptions\n\nLab 1: Using the PlanAhead Tool and Core Inserter Flows – Perform the same fundamental task twice: once with the ChipScope Pro tool core inserter and then with the PlanAhead™ tool. Lab 2: Using the Core Generator Flow – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the ChipScope Pro Analyzer tool.Lab 3: Using the Analyzer Tool – Configure triggers and view captured data using a completed design (including the bitstream).Lab 4: Tips and Tricks – Sample across multiple sample windows using a custom “sample-on-change” core and using the keep attribute to preserve signals. Observe the use of unconventional techniques to create triggers.Lab 5: Data Collection and Storage – Diagnose a design flaw using the ChipScope Pro tools via a practical example, focusing on the design diagnostics available from the tools. Lab 6: Scripting – Insert a core and set up automated analysis.Lab 7: Remote Access – Use the ChipScope Pro Analyzer tool to configure an FPGA, set up triggering, and view the sampled data from a remote location.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_76 DTSTAMP:20090828T201525 DTSTART:20091201T160000Z DTEND:20091202T000000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 11.3 features, such as the Architecture Wizard, PlanAhead™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan®-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the PlanAhead tool and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan®-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and PlanAhead Tool – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_77 DTSTAMP:20090828T201726 DTSTART:20091202T160000Z DTEND:20091204T000000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Essentials of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformanceLab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate it into VHDL or Verilog source code, and implement the design.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement the design.Lab 3: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Versions of this lab are available for Xilinx XST and Synplify Pro software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_65 DTSTAMP:20090811T152822 DTSTART:20091208T160000Z DTEND:20091211T000000Z CATEGORIES:FPGA Design SUMMARY:Designing with the Spartan-6 and Virtex-6 Families DESCRIPTION:Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families. Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced. This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught. \n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe all the functionality of the 6-input LUT and the CLB construction of the Spartan-6 and Virtex-6 FPGAsSpecify the CLB resources and the available slice configurations for the Spartan-6 and Virtex-6 FPGAsDefine the block RAM and DSP resources available for Spartan-6 and Virtex-6 FPGAsProperly design for the I/O block and SERDES resources Identify the DCM, PLL, and clock routing resources included with each of these familiesIdentify the supported memory controllers for the Spartan-6 and Virtex-6 FPGAsProperly code your HDL to get the most out of these devicesDescribe the additional dedicated hardware for all the Spartan-6 and Virtex-6 families\n\n Course OutlineDay 1\n\nSpartan-6 FPGA OverviewVirtex-6 FPGA OverviewCLB ArchitectureLab 1: CLB Resources Spartan-6 and Virtex-6 FPGA Memory ResourcesSpartan-6 and Virtex-6 FPGA DSP Resources \n\nDay 2\n\nLab 2: DSP Resources Basic I/O ResourcesSpartan-6 FPGA I/O ResourcesVirtex-6 FPGA I/O ResourcesLab 3: I/O ResourcesBasic Clocking ResourcesSpartan-6 FPGA Clocking Resources\n\nDay 3\n\nVirtex-6 FPGA Clocking ResourcesLab 4: Clocking Resources Spartan-6 and Virtex-6 FPGA Memory ControllersHDL Coding TechniquesLab 5: HDL Coding Techniques Dedicated Hardware in Spartan-6 and Virtex-6 FPGAs \n\nLab Descriptions\n\nLab 1: CLB Resources – Gain comprehensive experience with the CLB architecture. Synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.Lab 2: DSP Resources – Using XST, synthesize and implement a 24x17 MAC. Device usage will be verified via the FPGA Editor. Using the CORE Generator™ tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.Lab 3: I/O Resources – Using the ISE tools, complete the construction of the transmit SERDES datapath. Explore, through simulation, the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the Spartan-6 or Virtex-6 FPGA tile used for construction of a high-speed interface.Lab 4: Block RAM Resources – Using the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.Lab 5: HDL Coding Techniques – Using XST, synthesize various components into the design and evaluate the impact that proper HDL coding techniques have on the size and speed of implementation results. \n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Guru Labs (801 North 500 West, Suite 202, Bountiful, UT 84010) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_79 DTSTAMP:20090828T202340 DTSTART:20100128T160000Z DTEND:20100130T000000Z CATEGORIES:FPGA Design SUMMARY:Designing with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.\n\nNote: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.After completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun the Design Rule Checker (DRC) and WASSO analysisImport HDL sources, elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placementInsert ChipScope™ Pro tool debug coresFloorplan the design to improve performance and consistencyUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse OutlineDay 1\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsRTL Development and AnalysisLab 3: RTL Development and AnalysisImplementing a Design Lab 4: Implementing with the PlanAhead Tool\n\nDay 2\n\nDesign AnalysisLab 5: Design AnalysisFloorplanning TechniquesLab 6: FloorplanningDebugging with the ChipScope ToolLab 7: Debugging with the ChipScope ToolProject Navigator Integration with the PlanAhead ToolLab 8: Using the PlanAhead Tool with Project NavigatorCourse Summary\n\nLab DescriptionsNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope™ Pro cores and tools. Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAhead tool integrated within the ISE software Project Navigator environment.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_82 DTSTAMP:20090828T203014 DTSTART:20100202T160000Z DTEND:20100203T000000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site END:VEVENT BEGIN:VEVENT UID:_1_103 DTSTAMP:20091202T190207 DTSTART:20100209T160000Z DTEND:20100211T000000Z CATEGORIES:FPGA Design SUMMARY:Designing with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.\n\nNote: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.After completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun the Design Rule Checker (DRC) and WASSO analysisImport HDL sources, elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placementInsert ChipScope™ Pro tool debug coresFloorplan the design to improve performance and consistencyUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse OutlineDay 1\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsRTL Development and AnalysisLab 3: RTL Development and AnalysisImplementing a Design Lab 4: Implementing with the PlanAhead Tool\n\nDay 2\n\nDesign AnalysisLab 5: Design AnalysisFloorplanning TechniquesLab 6: FloorplanningDebugging with the ChipScope ToolLab 7: Debugging with the ChipScope ToolProject Navigator Integration with the PlanAhead ToolLab 8: Using the PlanAhead Tool with Project NavigatorCourse Summary\n\nLab DescriptionsNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope™ Pro cores and tools. Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAhead tool integrated within the ISE software Project Navigator environment.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_109 DTSTAMP:20100201T220930 DTSTART:20100222T160000Z DTEND:20100224T000000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 11.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 11.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\n Create and edit a User Constraint File (UCF)Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesImplement designs via the Tcl command linePreserve design results by using SmartGuide™ technologyUse the PlanAhead™ tool to create area constraintsChange signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor\n\nCourse Outline\n\n IntroductionLab 1: Timing Closure ReviewUCF EditingLab 2: UCF EditingAdvanced I/O TimingLab 3: Advanced I/O TimingTcl ScriptingLab 4: Tcl ScriptingSmartCompile™ Technology Design Preservation TechniquesLab 5: SmartGuide TechnologyFloorplanning an Effective LayoutLab 6: FloorplanningFPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor \n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 11.1 software. \n\n Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 3: Advanced I/O Timing – Compose timing constraints for an I/O interface. Analyze the timing and determine changes to optimize the interface timing.Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to enhance the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores. \n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_88 DTSTAMP:20090828T204742 DTSTART:20100225T160000Z DTEND:20100227T000000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 11.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 11.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\n Create and edit a User Constraint File (UCF)Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesImplement designs via the Tcl command linePreserve design results by using SmartGuide™ technologyUse the PlanAhead™ tool to create area constraintsChange signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor\n\nCourse Outline\n\n IntroductionLab 1: Timing Closure ReviewUCF EditingLab 2: UCF EditingAdvanced I/O TimingLab 3: Advanced I/O TimingTcl ScriptingLab 4: Tcl ScriptingSmartCompile™ Technology Design Preservation TechniquesLab 5: SmartGuide TechnologyFloorplanning an Effective LayoutLab 6: FloorplanningFPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor \n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 11.1 software. \n\n Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 3: Advanced I/O Timing – Compose timing constraints for an I/O interface. Analyze the timing and determine changes to optimize the interface timing.Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to enhance the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores. \n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_85 DTSTAMP:20090828T203427 DTSTART:20100301T160000Z DTEND:20100303T000000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\n\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_119 DTSTAMP:20100601T191450 DTSTART:20100616T150000Z DTEND:20100616T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the I/O Planner to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_139 DTSTAMP:20100611T154245 DTSTART:20100628T150000Z DTEND:20100630T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing for Performance" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_123 DTSTAMP:20100601T193050 DTSTART:20100715T150000Z DTEND:20100716T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsPath-Specific Timing Constraints, Part 1Path-Specific Timing Constraints, Part 2Lab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_126 DTSTAMP:20100601T194648 DTSTART:20100726T150000Z DTEND:20100727T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the Spartan®-6 and Virtex®-6 FPGAs.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nCreate and edit a User Constraint File (UCF)Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesImplement designs via the Tcl command linePreserve design results by using SmartGuide™ technology Use the PlanAhead™ tool to create area constraintsChange signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor\n\nCourse Outline\n\nIntroductionLab 1: Timing Closure Review UCF EditingLab 2: UCF EditingAdvanced I/O TimingLab 3: Advanced I/O TimingTcl ScriptingLab 4: Tcl ScriptingSmartGuide Technology Lab 5: SmartGuide TechnologyFloorplanning an Effective LayoutLab 6: Floorplanning FPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor\n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 12.1 software. \n\nLab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_125 DTSTAMP:20100601T193339 DTSTART:20100729T150000Z DTEND:20100730T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the Spartan®-6 and Virtex®-6 FPGAs.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nCreate and edit a User Constraint File (UCF)Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesImplement designs via the Tcl command linePreserve design results by using SmartGuide™ technology Use the PlanAhead™ tool to create area constraintsChange signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor\n\nCourse Outline\n\nIntroductionLab 1: Timing Closure Review UCF EditingLab 2: UCF EditingAdvanced I/O TimingLab 3: Advanced I/O TimingTcl ScriptingLab 4: Tcl ScriptingSmartGuide Technology Lab 5: SmartGuide TechnologyFloorplanning an Effective LayoutLab 6: Floorplanning FPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor\n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 12.1 software. \n\nLab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_130 DTSTAMP:20100601T201848 DTSTART:20100804T150000Z DTEND:20100804T230000Z CATEGORIES:FPGA Design SUMMARY:Essential Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and a demonstration.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun DRC and SSN noise analysisIntegrate IP with the PlanAhead toolImport HDL sources, elaborate, and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics and timingUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse Outline\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsCORE Generator Tool IntegrationLab 3: CORE Generator Tool IntegrationProject Navigator Integration Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead tool so that you can synthesize, add timing constraints, implement, perform timing analysis, and generate a bitstream. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PlanAhead tool’s pin planning environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, make clock logic placement, and make pin assignments.Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator tool with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_134 DTSTAMP:20100601T203105 DTSTART:20100805T150000Z DTEND:20100806T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable performance by using the PlanAhead™ software tool. Topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demonstrations.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentRun the RTL Design Rule Checker (DRC)Import HDL sources and elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placement, and timing critical pathsInsert ChipScope Pro tool debug coresFloorplan the design to improve performance and maintain successful implementation results\n\nCourse Outline\n\nDay 1\n\nPlanAhead Software ReviewLab 1: PlanAhead Software ReviewRTL Development and AnalysisLab 2: RTL Design AnalysisPblocksFloorplanning Techniques Lab 3: Design Analysis and Floorplanning for Performance\n\nDay 2\n\nDesign Preservation with PartitionsLab 4: Leveraging Design Preservation for Predictable Results Debugging with the ChipScope Pro Tool and PlanAhead SoftwareLab 5: Debugging with the ChipScope Pro ToolCourse Summary\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: PlanAhead Software Review – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: RTL Design Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).Lab 3: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 4: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.Lab 5: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_141 DTSTAMP:20100719T144853 DTSTART:20100819T150000Z DTEND:20100819T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Essentials of FPGA Design" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_145 DTSTAMP:20100802T192133 DTSTART:20100908T150000Z DTEND:20100908T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the I/O Planner to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_122 DTSTAMP:20100601T192848 DTSTART:20100909T150000Z DTEND:20100910T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsPath-Specific Timing Constraints, Part 1Path-Specific Timing Constraints, Part 2Lab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_148 DTSTAMP:20100802T193552 DTSTART:20100923T150000Z DTEND:20100924T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsPath-Specific Timing Constraints, Part 1Path-Specific Timing Constraints, Part 2Lab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Salt Lake City, UT (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_131 DTSTAMP:20100601T201948 DTSTART:20100928T150000Z DTEND:20100928T230000Z CATEGORIES:FPGA Design SUMMARY:Essential Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and a demonstration.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun DRC and SSN noise analysisIntegrate IP with the PlanAhead toolImport HDL sources, elaborate, and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics and timingUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse Outline\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsCORE Generator Tool IntegrationLab 3: CORE Generator Tool IntegrationProject Navigator Integration Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead tool so that you can synthesize, add timing constraints, implement, perform timing analysis, and generate a bitstream. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PlanAhead tool’s pin planning environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, make clock logic placement, and make pin assignments.Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator tool with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_135 DTSTAMP:20100601T203146 DTSTART:20100929T150000Z DTEND:20100930T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable performance by using the PlanAhead™ software tool. Topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demonstrations.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentRun the RTL Design Rule Checker (DRC)Import HDL sources and elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placement, and timing critical pathsInsert ChipScope Pro tool debug coresFloorplan the design to improve performance and maintain successful implementation results\n\nCourse Outline\n\nDay 1\n\nPlanAhead Software ReviewLab 1: PlanAhead Software ReviewRTL Development and AnalysisLab 2: RTL Design AnalysisPblocksFloorplanning Techniques Lab 3: Design Analysis and Floorplanning for Performance\n\nDay 2\n\nDesign Preservation with PartitionsLab 4: Leveraging Design Preservation for Predictable Results Debugging with the ChipScope Pro Tool and PlanAhead SoftwareLab 5: Debugging with the ChipScope Pro ToolCourse Summary\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: PlanAhead Software Review – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: RTL Design Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).Lab 3: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 4: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.Lab 5: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_129 DTSTAMP:20100601T201744 DTSTART:20101006T150000Z DTEND:20101006T230000Z CATEGORIES:FPGA Design SUMMARY:Essential Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and a demonstration.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun DRC and SSN noise analysisIntegrate IP with the PlanAhead toolImport HDL sources, elaborate, and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics and timingUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse Outline\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsCORE Generator Tool IntegrationLab 3: CORE Generator Tool IntegrationProject Navigator Integration Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead tool so that you can synthesize, add timing constraints, implement, perform timing analysis, and generate a bitstream. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PlanAhead tool’s pin planning environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, make clock logic placement, and make pin assignments.Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator tool with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Austin, TX (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_133 DTSTAMP:20100601T203011 DTSTART:20101007T150000Z DTEND:20101008T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable performance by using the PlanAhead™ software tool. Topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demonstrations.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentRun the RTL Design Rule Checker (DRC)Import HDL sources and elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placement, and timing critical pathsInsert ChipScope Pro tool debug coresFloorplan the design to improve performance and maintain successful implementation results\n\nCourse Outline\n\nDay 1\n\nPlanAhead Software ReviewLab 1: PlanAhead Software ReviewRTL Development and AnalysisLab 2: RTL Design AnalysisPblocksFloorplanning Techniques Lab 3: Design Analysis and Floorplanning for Performance\n\nDay 2\n\nDesign Preservation with PartitionsLab 4: Leveraging Design Preservation for Predictable Results Debugging with the ChipScope Pro Tool and PlanAhead SoftwareLab 5: Debugging with the ChipScope Pro ToolCourse Summary\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: PlanAhead Software Review – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: RTL Design Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).Lab 3: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 4: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.Lab 5: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Austin, TX (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_149 DTSTAMP:20100802T194147 DTSTART:20101011T150000Z DTEND:20101011T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the I/O Planner to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_150 DTSTAMP:20100802T194253 DTSTART:20101012T150000Z DTEND:20101013T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsPath-Specific Timing Constraints, Part 1Path-Specific Timing Constraints, Part 2Lab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT END:VCALENDAR

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