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Course Calendar

BEGIN:VCALENDAR VERSION:2.0 PRODID:-//TYPO3/NONSGML Calendar Base (cal) V1.2.0//EN METHOD:PUBLISH BEGIN:VEVENT UID:_1_6 DTSTAMP:20090302T201939 DTSTART:20090317T150000Z DTEND:20090317T203000Z CATEGORIES:General SUMMARY:RTECC Dallas DESCRIPTION:The Real-Time & Embedded Computing Conference (RTECC) is a single-day conference and exhibition showcase focused for people that are developing computer systems and time-critical applications serving multiple industries; this includes: industrial control, data communication and telephony, military and aerospace, instrumentation, consumer electronics, image processing, process control, vehicular control and maintenance, embedded appliances and more. \n\nRTECC is suited to meet the needs of Software and Hardware Engineers, both design and Production, R&D, Electrical and Electronic Engineers, Project Engineers, Directors and Managers of Engineering by design. The table-top product showcase is arranged for easy vendor and product comparisons. The open-door technical seminars and workshops allow attendees a valuable learning opportunity and time to talk in depth with technical experts.\n\nRTECC events bring core emerging technologies - the top subjects on the minds of developers, to over 30 cities around the world. Every event is arranged to meet and exchange ideas with the best and brightest in the industry. \n\nRTECC Dallas Brochure LOCATION:Renaissance Dallas Richardson Hotel ORGANIZER;CN="The Real-Time & Embedded Computing Conferences": END:VEVENT BEGIN:VEVENT UID:_1_5 DTSTAMP:20090302T201758 DTSTART:20090319T150000Z DTEND:20090319T203000Z CATEGORIES:General SUMMARY:RTECC Austin DESCRIPTION:The Real-Time & Embedded Computing Conference (RTECC) is a single-day conference and exhibition showcase focused for people that are developing computer systems and time-critical applications serving multiple industries; this includes: industrial control, data communication and telephony, military and aerospace, instrumentation, consumer electronics, image processing, process control, vehicular control and maintenance, embedded appliances and more. \n\nRTECC is suited to meet the needs of Software and Hardware Engineers, both design and Production, R&D, Electrical and Electronic Engineers, Project Engineers, Directors and Managers of Engineering by design. The table-top product showcase is arranged for easy vendor and product comparisons. The open-door technical seminars and workshops allow attendees a valuable learning opportunity and time to talk in depth with technical experts.\n\nRTECC events bring core emerging technologies - the top subjects on the minds of developers, to over 30 cities around the world. Every event is arranged to meet and exchange ideas with the best and brightest in the industry. \n\nRTECC Austin Brochure LOCATION:Crowne Plaza Hotel - Austin ORGANIZER;CN="The Real-Time & Embedded Computing Conferences": END:VEVENT BEGIN:VEVENT UID:_1_17 DTSTAMP:20090330T193955 DTSTART:20090429T150000Z DTEND:20090429T230000Z CATEGORIES:FPGA Design SUMMARY:Fundamentals of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE 10.1 features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.Note that one of the prerequisites of Fundamentals of FPGA Design is the completion of the basic FPGA architecture modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to:\n\nUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Architecture Wizard to create DCM instantiationsUse the Floorplan Editor and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraintsLocate and modify the implementation options\n\nCourse Outline\n\nCourse AgendaXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Architecture Wizard and Floorplan Editor/PACE Lab 3: Pre-Assigning I/O Pins Using PinAhead Global Timing ConstraintsLab 4: Global Timing Constraints Implementation OptionsLab 5: Implementation Options Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the Architecture Wizard and the Floorplan Editor or PACE in the design process. Implement a design by using default software options. The design will be simulated and downloaded to a Spartan®-3E FPGA 1600 demo board.Lab 2: Architecture Wizard and Floorplan Editor/PACE – Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design.Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.Lab 5: Implementation Options – Adjust process properties and I/O configuration options to improve the design performance.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_13 DTSTAMP:20090401T160642 DTSTART:20090430T150000Z DTEND:20090501T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.Note that one of the prerequisites of Designing for Performance is the completion of the HDL coding style modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Fundamentals of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformancePower Estimation (Optional)Lab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources.Lab 3: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:(TBD) Dallas, TX END:VEVENT BEGIN:VEVENT UID:_1_24 DTSTAMP:20090424T183434 DTSTART:20090527T150000Z DTEND:20090529T230000Z CATEGORIES:Languages SUMMARY:Introduction to VHDL DESCRIPTION:This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectureswith practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.\n\nIn this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nWrite RTL VHDL code for synthesisWrite VHDL testbenches for simulationCreate Finite State Machines (FSMs) by using VHDLTarget and optimize Xilinx FPGAs by using VHDLCreate RAM and ROM data structuresUse VHDL scalar and composite data typesRun a simulation by using VITAL librariesUse the VHDL textio package during simulationCreate and manage designs within the ISE software design environment \n\n Course OutlineDay 1\n\nCourse AgendaHardware Modeling OverviewVHDL Language ConceptsLab 1: Building HierarchyIntroduction to TestbenchesLab 2: VHDL Simulation and RTL VerificationSignals and Data TypesVHDL Operators and ExpressionsLab 3: Memory\n\nDay 2\n\nConcurrent and Sequential StatementsLab 4: Clock Divider and Address CounterControlled Operation StatementsLab 5: n-bit Binary Counter and RTL VerificationVITAL: VHDL Initiative toward ASIC LibrariesLab 6: Timing SimulationBehavioral to RTL Coding\n\nDay 3\n\nFinite State MachinesLab 7: Finite State MachinesTargeting Xilinx FPGAsLab 8: Implement and DownloadFunctions and ProceduresAdvanced Process StatementsLab 9: Text I/O\n\nLab Descriptions\n\nThe labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that you will verify in simulation.\n\nRegister Today\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_25 DTSTAMP:20090427T152756 DTSTART:20090601T150000Z DTEND:20090601T230000Z CATEGORIES:FPGA Design SUMMARY:Fundamentals of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE 10.1 features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.Note that one of the prerequisites of Fundamentals of FPGA Design is the completion of the basic FPGA architecture modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to:\n\nUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Architecture Wizard to create DCM instantiationsUse the Floorplan Editor and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraintsLocate and modify the implementation options\n\nCourse Outline\n\nCourse AgendaXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Architecture Wizard and Floorplan Editor/PACE Lab 3: Pre-Assigning I/O Pins Using PinAhead Global Timing ConstraintsLab 4: Global Timing Constraints Implementation OptionsLab 5: Implementation Options Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the Architecture Wizard and the Floorplan Editor or PACE in the design process. Implement a design by using default software options. The design will be simulated and downloaded to a Spartan®-3E FPGA 1600 demo board.Lab 2: Architecture Wizard and Floorplan Editor/PACE – Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design.Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.Lab 5: Implementation Options – Adjust process properties and I/O configuration options to improve the design performance.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_27 DTSTAMP:20090427T153208 DTSTART:20090602T150000Z DTEND:20090603T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.Note that one of the prerequisites of Designing for Performance is the completion of the HDL coding style modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Fundamentals of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformancePower Estimation (Optional)Lab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources.Lab 3: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_29 DTSTAMP:20090427T153425 DTSTART:20090604T150000Z DTEND:20090605T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 10.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 10.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.After completing this comprehensive training, you will have the necessary skills to: \n\nImplement designs via the Tcl command lineCreate and edit timing constraints in the UCF fileIdentify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesPreserve design results by using SmartGuide™ technology or partitionsUse the Floorplan Editor or Pinout and Area Constraints Editor (PACE) to create area constraintsChange signals of interest in the ChipScope™ Pro tool for boardlevel debugging using the FPGA Editor\n\nCourse Outline\n\n IntroductionLab 1: Achieving Timing Closure and Review of Global Timing ConstraintsTcl ScriptingLab 2: Tcl ScriptingUCF EditingLab 3: UCF EditingAdvanced I/O TimingLab 4: Advanced I/O TimingSmartCompile™ Technology Design Preservation TechniquesLab 5: SmartCompile TechnologyFloorplanning an Effective LayoutLab 6: FloorplanningFPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor\n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 10.1 software. \n\n Lab 1: Achieving Timing Closure and Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 2: Tcl Scripting – Write ISE tool control commands in a Tcl script file to implement the design. Then modify program switches to obtain the greatest possible performance from the design.Lab 3: UCF – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 4: Advanced I/O Timing – Compose timing constraints for an I/O interface. Analyze the timing failures and determine changes to correct the timing issues. Modify the design to fix timing failures.Lab 5: SmartCompile Technology – Utilize SmartGuide technology and partitions to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to enhance the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:BP Sales - Corporate Headquarters (2201 N Central Expy, Suite 255, Richardson, TX 75080) END:VEVENT BEGIN:VEVENT UID:_1_32 DTSTAMP:20090615T164042 DTSTART:20090623T150000Z DTEND:20090624T230000Z CATEGORIES:General SUMMARY:Custom Onsite Training DESCRIPTION:Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include:\n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nWe can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nPrivate Class Request Turnaround Time: Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. END:VEVENT BEGIN:VEVENT UID:_1_34 DTSTAMP:20090615T172412 DTSTART:20090713T150000Z DTEND:20090713T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:\n\nUse the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.\n\n \n\nThis course covers ISE software 11.1 features, such as the Architecture Wizard, PlanAhead™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. \n\n \n\nFor more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.Use\n\nthe ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE 10.1 features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.Note that one of the prerequisites of Fundamentals of FPGA Design is the completion of the basic FPGA architecture modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.After completing this comprehensive training, you will have the necessary skills to:\n\nUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Architecture Wizard to create DCM instantiationsUse the Floorplan Editor and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraintsLocate and modify the implementation options\n\nCourse Outline\n\nCourse AgendaXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Architecture Wizard and Floorplan Editor/PACE Lab 3: Pre-Assigning I/O Pins Using PinAhead Global Timing ConstraintsLab 4: Global Timing Constraints Implementation OptionsLab 5: Implementation Options Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the Architecture Wizard and the Floorplan Editor or PACE in the design process. Implement a design by using default software options. The design will be simulated and downloaded to a Spartan®-3E FPGA 1600 demo board.Lab 2: Architecture Wizard and Floorplan Editor/PACE – Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design.Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.Lab 5: Implementation Options – Adjust process properties and I/O configuration options to improve the design performance.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_35 DTSTAMP:20090615T174332 DTSTART:20090714T150000Z DTEND:20090715T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Essentials of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformanceLab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate it into VHDL or Verilog source code, and implement the design.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement the design.Lab 3: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Versions of this lab are available for Xilinx XST and Synplify Pro software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nTo sign up for this class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Class Registration page. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) END:VEVENT BEGIN:VEVENT UID:_1_46 DTSTAMP:20090727T153131 DTSTART:20090810T150000Z DTEND:20090811T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Registration for this course is available through our Online Store.\n\nXilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the EDK environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse OutlineDay 1\n\n EDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading SoftwareSystem BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\n Interfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building a Custom IP Peripheral for an Embedded System – PLB v46 BusBus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions Both the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the Virtex®-5 FPGA ML507 and Spartan®-3E FPGA boards.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design.Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the board.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building a Custom IP Peripheral for an Embedded System – Create and add custom IP (IPIC interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in the design.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_55 DTSTAMP:20090727T203627 DTSTART:20090916T150000Z DTEND:20090916T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.\n\nThis course covers ISE software 11.1 features, such as the Architecture Wizard, PlanAhead™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. \n\nFor more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Virtex®-5 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Architecture Wizard to create DCM instantiationsUse the PlanAhead tool and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Architecture Wizard Lab 3: Pre-Assigning I/O Pins Using PinAhead Global Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan®-3E FPGA 1600 demo board. Lab 2: Architecture Wizard and PlanAhead Tool – Use the Architecture Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_56 DTSTAMP:20090727T203921 DTSTART:20090917T150000Z DTEND:20090918T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Essentials of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformanceLab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate it into VHDL or Verilog source code, and implement the design.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement the design.Lab 3: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Versions of this lab are available for Xilinx XST and Synplify Pro software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_94 DTSTAMP:20090918T193813 DTSTART:20091020T140000Z DTEND:20091020T223000Z CATEGORIES:General SUMMARY:X-Fest DESCRIPTION:From October 2009 through February 2010, X-fest events will be hosted in 37 locations throughout Asia, Europe, North America and Japan. X-fest is a global series of FREE technical seminars, offering practical, how-to training for designers interested in using the new Spartan®-6 and Virtex®-6 FPGA families from Xilinx.These full-day events will showcase innovative design techniques, methodologies and implementations as well as reference designs from multiple manufacturers that can accelerate myriad applications from PCIe to video to wireless to embedded networking and more!Don't miss this opportunity to learn how to maximize next generation FPGAs and to improve your design capabilities. Seating is limited so register today! END:VEVENT BEGIN:VEVENT UID:_1_92 DTSTAMP:20090915T150024 DTSTART:20091020T150000Z DTEND:20091021T230000Z CATEGORIES:Embedded Design SUMMARY:Advanced Embedded Systems Development DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site END:VEVENT BEGIN:VEVENT UID:_1_61 DTSTAMP:20090727T211023 DTSTART:20091028T150000Z DTEND:20091028T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 11.3 features, such as the Architecture Wizard, PlanAhead™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan®-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the PlanAhead tool and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan®-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and PlanAhead Tool – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_62 DTSTAMP:20090727T211128 DTSTART:20091029T150000Z DTEND:20091030T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Essentials of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformanceLab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate it into VHDL or Verilog source code, and implement the design.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement the design.Lab 3: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Versions of this lab are available for Xilinx XST and Synplify Pro software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_95 DTSTAMP:20090918T194210 DTSTART:20091103T150000Z DTEND:20091103T233000Z CATEGORIES:General SUMMARY:X-Fest DESCRIPTION:From October 2009 through February 2010, X-fest events will be hosted in 37 locations throughout Asia, Europe, North America and Japan. X-fest is a global series of FREE technical seminars, offering practical, how-to training for designers interested in using the new Spartan®-6 and Virtex®-6 FPGA families from Xilinx.These full-day events will showcase innovative design techniques, methodologies and implementations as well as reference designs from multiple manufacturers that can accelerate myriad applications from PCIe to video to wireless to embedded networking and more!Don't miss this opportunity to learn how to maximize next generation FPGAs and to improve your design capabilities. Seating is limited so register today! END:VEVENT BEGIN:VEVENT UID:_1_70 DTSTAMP:20090828T150247 DTSTART:20091105T160000Z DTEND:20091107T000000Z CATEGORIES:DSP Design SUMMARY:DSP Design Using System Generator DESCRIPTION:This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nDescribe the System Generator design flow for implementing DSP functionsIdentify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulationList various low-level and high-level functional blocks available in System GeneratorIdentify the high-level blocks available for FIR and FFT designsDesign a multiple-clock-based System Generator systemEmbed two System Generator designs into a larger design\n\nCourse OutlineDay 1\n\nIntroduction to System GeneratorSimulink Software BasicsLab 1: Using the Simulink SoftwareBasic Xilinx Design CaptureLab 2: Getting Started with Xilinx System GeneratorSignal RoutingLab 3: Signal RoutingImplementing System ControlLab 4: Implementing System Control\n\nDay 2\n\nMulti-Rate SystemsLab 5: Designing a MAC-Based FIR Filter DesignLab 6: Designing a FIR Filter Using the FIR Compiler Block Xilinx System Generator, Project Navigator, and Platform Studio IntegrationLab 7: System Generator and Project Navigator IntegrationLab 8: System Generator, Project Navigator, and Platform Studio Integration\n\nLab Descriptions\n\nLab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based (ML505 board) design. Perform hardware co-simulation verification targeting an ML505 board.Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using an ML505 board.Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using the ML505 board.Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.Lab 8: System Generator, Project Navigator, and Platform Studio Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_63 DTSTAMP:20090810T171415 DTSTART:20091109T160000Z DTEND:20091111T000000Z CATEGORIES:FPGA Design SUMMARY:Designing with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.\n\nNote: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.After completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun the Design Rule Checker (DRC) and WASSO analysisImport HDL sources, elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placementInsert ChipScope™ Pro tool debug coresFloorplan the design to improve performance and consistencyUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse OutlineDay 1\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsRTL Development and AnalysisLab 3: RTL Development and AnalysisImplementing a Design Lab 4: Implementing with the PlanAhead Tool\n\nDay 2\n\nDesign AnalysisLab 5: Design AnalysisFloorplanning TechniquesLab 6: FloorplanningDebugging with the ChipScope ToolLab 7: Debugging with the ChipScope ToolProject Navigator Integration with the PlanAhead ToolLab 8: Using the PlanAhead Tool with Project NavigatorCourse Summary\n\nLab DescriptionsNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope™ Pro cores and tools. Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAhead tool integrated within the ISE software Project Navigator environment.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_64 DTSTAMP:20090811T151921 DTSTART:20091111T160000Z DTEND:20091113T000000Z CATEGORIES:FPGA Design SUMMARY:Debugging Techniques Using the ChipScope Pro Tools DESCRIPTION:As FPGA designs become increasingly more complex, designers are looking to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for debug and verification. This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nMaximize ChipScope Pro tool core performanceMinimize negative timing impacts on a designEffectively utilize the various sampling coresVisualize captured data in the most advantageous fashionUse techniques that enhance and extend the capabilities of the ChipScope Pro toolsExecute remote debugging\n\nCourse OutlineDay 1 \n\nAgenda and IntroductionHow the ChipScope Pro Tool WorksInserting the Core Using Core Inserter and the PlanAhead SoftwareLab 1: Using the PlanAhead Tool and Core Inserter FlowsInstantiating the CoresLab 2: Using the Core Generator Flow Triggering Methods and Maximizing StorageVisualizing the Sampled Data Lab 3: Using the Analyzer ToolDay 1 Summary\n\nDay 2\n\nDay 2 IntroductionTips and TricksLab 4: Tips and TricksTime for TimingVideo Demo: Area Groups and the ChipScope Pro ToolCase StudiesLab 5: Data Collection and StorageScripting (Optional)*Lab 6: Scripting (Optional)*Remote Access (Optional)*Lab 7: Remote Access (Optional)*Summary\n\n\n\n* Please check with your ATP to confirm whether this content is included with your specific class.\n\nLab Descriptions\n\nLab 1: Using the PlanAhead Tool and Core Inserter Flows – Perform the same fundamental task twice: once with the ChipScope Pro tool core inserter and then with the PlanAhead™ tool. Lab 2: Using the Core Generator Flow – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the ChipScope Pro Analyzer tool.Lab 3: Using the Analyzer Tool – Configure triggers and view captured data using a completed design (including the bitstream).Lab 4: Tips and Tricks – Sample across multiple sample windows using a custom “sample-on-change” core and using the keep attribute to preserve signals. Observe the use of unconventional techniques to create triggers.Lab 5: Data Collection and Storage – Diagnose a design flaw using the ChipScope Pro tools via a practical example, focusing on the design diagnostics available from the tools. Lab 6: Scripting – Insert a core and set up automated analysis.Lab 7: Remote Access – Use the ChipScope Pro Analyzer tool to configure an FPGA, set up triggering, and view the sampled data from a remote location.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_96 DTSTAMP:20091001T163658 DTSTART:20091116T160000Z DTEND:20091118T000000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the EDK environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse OutlineDay 1\n\n EDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading SoftwareSystem BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\n Interfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building a Custom IP Peripheral for an Embedded System – PLB v46 BusBus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions Both the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the Virtex®-5 FPGA ML507 and Spartan®-3E FPGA boards.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design.Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the board.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building a Custom IP Peripheral for an Embedded System – Create and add custom IP (IPIC interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in the design.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_72 DTSTAMP:20090828T162232 DTSTART:20091118T160000Z DTEND:20091120T000000Z CATEGORIES:Embedded Design SUMMARY:Advanced Embedded Systems Development DESCRIPTION:Advanced Features and Techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system. This course builds on the skills gained in the Embedded Systems Development course. Labs provide hands-on experience with the development, verification, debugging, and simulation of an embedded system. Some labs use the Virtex®-5 FPGA ML507 demo board in which designs are downloaded and verified.After completing this comprehensive training, you will have the necessary skills to: \n\nAssemble an advanced embedded systemTake advantage of the various Virtex-5 FPGA and PowerPC® 440 processor features, including the crossbar and multi-port memory controllerApply advanced debugging techniques, including the use of the ChipScope™ tool for debugging an embedded system and HDL system simulationIdentify the steps involved in integrating a memory controller into an embedded system using the PowerPC 440 processorIntegrate an interrupt controller and interrupt handler into your embedded designDesign a Flash memory-based system and boot load from off-chip Flash memory Perform HDL-based system simulation\n\nCourse OutlineDay 1\n\nEmbedded Systems Development ReviewLab 1: Building a Complete Embedded SystemPowerPC 440 Processor CrossbarDebugging Using the ChipScope Pro AnalyzerLab 2: Debugging Using the ChipScope Pro AnalyzerBlock RAM Memory ControllersMulti-Channel External Memory Controller for Static MemoryPowerPC 440 Processor DDR2 Memory Controller for the Crossbar MCIMulti-Port Memory Controller for Dynamic RAMLab 3: Instantiating a DDR2 Memory Controller\n\nDay 2\n\nInterruptsFast Simplex LinksAdvanced Processor and Peripheral Interface OptionsLab 4: Interfacing an Embedded System to FPGA FabricAdvanced Processor ConfigurationsBoot LoaderLab 5: Boot Loading from Flash MemoryHDL System Simulation in XPSLab 6: Simulating an Embedded Processor System\n\nLab Descriptions \n\nLab 1: Building a Complete Embedded System – Develop hardware that incorporates IP cores to interface to push buttons, switches, LEDs, an LCD display, and serial communication. Develop an application that interacts with switches, push buttons, an LCD display, and serial communication. Generate and download a bitstream onto the ML507 demo board.Lab 2: Debugging Using the ChipScope Pro Analyzer – Perform simultaneous hardware and software debugging with the ChipScope™ Pro Analyzer, SDK Debug perspective, and XMD.Lab 3: Instantiating a DDR2 Memory Controller – Use XPS to instantiate a DDR2 memory controller. Explore memory device parameter configurations and proper memory controller clocking procedures.Lab 4: Interfacing an Embedded System to FPGA Fabric – Move data between an embedded system and FPGA fabric via an FSL and a dual-port block RAM. Implement an interrupt controller and an interrupt handler.Lab 5: Boot Loading from Flash Memory – Develop an application that is stored in flash memory, load it through a boot loader program, and execute the software from external memory. Lab 6: Simulating an Embedded Processor System – Set up and perform HDL-based simulation on an embedded processor system. Explore the tool flow for performing embedded processor simulation as part of a Project Navigator design in the ISE software.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_76 DTSTAMP:20090828T201525 DTSTART:20091201T160000Z DTEND:20091202T000000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 11.3 features, such as the Architecture Wizard, PlanAhead™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan®-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the PlanAhead tool and PinAhead to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan®-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and PlanAhead Tool – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_77 DTSTAMP:20090828T201726 DTSTART:20091202T160000Z DTEND:20091204T000000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe a flow for obtaining timing closure Describe architectural features of the Virtex-5 FPGADescribe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceCreate and integrate cores into your design flow by using the CORE Generator™ software systemRun behavioral simulation on an FPGA design that contains coresPinpoint design bottlenecks by using the Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse OutlineDay 1\n\nReview of Essentials of FPGA DesignDesigning with Virtex-5 FPGA ResourcesCORE Generator Software SystemLab 1: CORE Generator Software System Designing Clock ResourcesLab 2: Designing Clock ResourcesFPGA Design TechniquesSynthesis TechniquesLab 3: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 4: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 5: Achieving Timing ClosureAdvanced Implementation OptionsLab 6: Designing for PerformanceLab 7: FPGA Editor Demo (Optional)ChipScope Pro Software (Optional)Lab 8: ChipScope Pro Software (Optional)\n\nLab Descriptions\n\nLab 1: CORE Generator Software System – Create a core, instantiate it into VHDL or Verilog source code, and implement the design.Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement the design.Lab 3: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Versions of this lab are available for Xilinx XST and Synplify Pro software.Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_65 DTSTAMP:20090811T152822 DTSTART:20091208T160000Z DTEND:20091211T000000Z CATEGORIES:FPGA Design SUMMARY:Designing with the Spartan-6 and Virtex-6 Families DESCRIPTION:Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families. Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced. This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught. \n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe all the functionality of the 6-input LUT and the CLB construction of the Spartan-6 and Virtex-6 FPGAsSpecify the CLB resources and the available slice configurations for the Spartan-6 and Virtex-6 FPGAsDefine the block RAM and DSP resources available for Spartan-6 and Virtex-6 FPGAsProperly design for the I/O block and SERDES resources Identify the DCM, PLL, and clock routing resources included with each of these familiesIdentify the supported memory controllers for the Spartan-6 and Virtex-6 FPGAsProperly code your HDL to get the most out of these devicesDescribe the additional dedicated hardware for all the Spartan-6 and Virtex-6 families\n\n Course OutlineDay 1\n\nSpartan-6 FPGA OverviewVirtex-6 FPGA OverviewCLB ArchitectureLab 1: CLB Resources Spartan-6 and Virtex-6 FPGA Memory ResourcesSpartan-6 and Virtex-6 FPGA DSP Resources \n\nDay 2\n\nLab 2: DSP Resources Basic I/O ResourcesSpartan-6 FPGA I/O ResourcesVirtex-6 FPGA I/O ResourcesLab 3: I/O ResourcesBasic Clocking ResourcesSpartan-6 FPGA Clocking Resources\n\nDay 3\n\nVirtex-6 FPGA Clocking ResourcesLab 4: Clocking Resources Spartan-6 and Virtex-6 FPGA Memory ControllersHDL Coding TechniquesLab 5: HDL Coding Techniques Dedicated Hardware in Spartan-6 and Virtex-6 FPGAs \n\nLab Descriptions\n\nLab 1: CLB Resources – Gain comprehensive experience with the CLB architecture. Synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.Lab 2: DSP Resources – Using XST, synthesize and implement a 24x17 MAC. Device usage will be verified via the FPGA Editor. Using the CORE Generator™ tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.Lab 3: I/O Resources – Using the ISE tools, complete the construction of the transmit SERDES datapath. Explore, through simulation, the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the Spartan-6 or Virtex-6 FPGA tile used for construction of a high-speed interface.Lab 4: Block RAM Resources – Using the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.Lab 5: HDL Coding Techniques – Using XST, synthesize various components into the design and evaluate the impact that proper HDL coding techniques have on the size and speed of implementation results. \n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Guru Labs (801 North 500 West, Suite 202, Bountiful, UT 84010) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_78 DTSTAMP:20090828T202054 DTSTART:20100113T160000Z DTEND:20100116T000000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. END:VEVENT BEGIN:VEVENT UID:_1_100 DTSTAMP:20091103T180018 DTSTART:20100120T160000Z DTEND:20100122T000000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.After completing this comprehensive training, you will have the necessary skills to: \n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the EDK environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse OutlineDay 1\n\n EDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading SoftwareSystem BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\n Interfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building a Custom IP Peripheral for an Embedded System – PLB v46 BusBus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions Both the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the Virtex®-5 FPGA ML507 and Spartan®-3E FPGA boards.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design.Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the board.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building a Custom IP Peripheral for an Embedded System – Create and add custom IP (IPIC interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in the design.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_79 DTSTAMP:20090828T202340 DTSTART:20100128T160000Z DTEND:20100130T000000Z CATEGORIES:FPGA Design SUMMARY:Designing with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.\n\nNote: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.After completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun the Design Rule Checker (DRC) and WASSO analysisImport HDL sources, elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placementInsert ChipScope™ Pro tool debug coresFloorplan the design to improve performance and consistencyUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse OutlineDay 1\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsRTL Development and AnalysisLab 3: RTL Development and AnalysisImplementing a Design Lab 4: Implementing with the PlanAhead Tool\n\nDay 2\n\nDesign AnalysisLab 5: Design AnalysisFloorplanning TechniquesLab 6: FloorplanningDebugging with the ChipScope ToolLab 7: Debugging with the ChipScope ToolProject Navigator Integration with the PlanAhead ToolLab 8: Using the PlanAhead Tool with Project NavigatorCourse Summary\n\nLab DescriptionsNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope™ Pro cores and tools. Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAhead tool integrated within the ISE software Project Navigator environment.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_82 DTSTAMP:20090828T203014 DTSTART:20100202T160000Z DTEND:20100203T000000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site END:VEVENT BEGIN:VEVENT UID:_1_101 DTSTAMP:20091202T174715 DTSTART:20100202T160000Z DTEND:20100205T000000Z CATEGORIES:Connectivity SUMMARY:Signal Integrity and Board Design for Xilinx FPGAs DESCRIPTION:Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design technique and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe signal integrity effectsPredict and overcome signal integrity challenges Simulate signal integrity effectsVerify and derive design rules for the board designApply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and semiconductor circuitsPlan your board design under FPGA-specific restrictionsSupply the FPGAs with powerHandle thermal aspects\n\n Course OutlinePart 1 - Signal Integrity\n\nSignal Integrity IntroductionTransmission LinesIBIS Models and SI ToolsLab 1: Invoking HyperLynxReflectionsLab 2: Reflection AnalysisCrosstalkLab 3: Crosstalk AnalysisSignal Integrity AnalysisPower Supply IssuesSignal Integrity Summary\n\nPart 2 - Board Design\n\nBoard Design IntroductionFPGA Power SupplyLab 4: Power PredictionFPGA Configuration and PCBSignal Interfacing: Interfacing in GeneralSignal Interfacing: FPGA-Specific Interfacing Lab 5: I/O Pin PlanningDie Architecture and PackagingPCB DetailsThermal AspectsLab 6: Thermal DesignTools for PCB Planning and DesignBoard Design Summary\n\nLab Descriptions\n\nLab 1: Invoking HyperLynx – Get familiar with signal integrity tools. Use HyperLynx for schematic entry, modeling, and simulation. Modify a standard IBIS model to define a driver and then use its stackup editor to define a PCB.Lab 2: Reflection Analysis – Define a circuit and run various simulations for effects of reflection.Lab 3: Crosstalk Analysis – Using simulation, analyze circuit topology and PCB data for strategies to minimize crosstalk.Lab 4: Power Prediction – Estimate initial power requirements using an Excel spreadsheet, then use XPower Analyzer to accurately predict board power needs.Lab 5: I/O Pin Planning – Use the ISE tools or PlanAhead software to identify pin placement and implement pin assignments.Lab 6: Thermal Design – Determine maximum junction temperature and calculate acceptable thermal resistance.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Courtyard Salt Lake City Airport (4843 West Douglas Corrigan Way, Salt Lake City, Utah 84116) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_103 DTSTAMP:20091202T190207 DTSTART:20100209T160000Z DTEND:20100211T000000Z CATEGORIES:FPGA Design SUMMARY:Designing with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.\n\nNote: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.After completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun the Design Rule Checker (DRC) and WASSO analysisImport HDL sources, elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placementInsert ChipScope™ Pro tool debug coresFloorplan the design to improve performance and consistencyUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse OutlineDay 1\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsRTL Development and AnalysisLab 3: RTL Development and AnalysisImplementing a Design Lab 4: Implementing with the PlanAhead Tool\n\nDay 2\n\nDesign AnalysisLab 5: Design AnalysisFloorplanning TechniquesLab 6: FloorplanningDebugging with the ChipScope ToolLab 7: Debugging with the ChipScope ToolProject Navigator Integration with the PlanAhead ToolLab 8: Using the PlanAhead Tool with Project NavigatorCourse Summary\n\nLab DescriptionsNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope™ Pro cores and tools. Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAhead tool integrated within the ISE software Project Navigator environment.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_109 DTSTAMP:20100201T220930 DTSTART:20100222T160000Z DTEND:20100224T000000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 11.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 11.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\n Create and edit a User Constraint File (UCF)Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesImplement designs via the Tcl command linePreserve design results by using SmartGuide™ technologyUse the PlanAhead™ tool to create area constraintsChange signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor\n\nCourse Outline\n\n IntroductionLab 1: Timing Closure ReviewUCF EditingLab 2: UCF EditingAdvanced I/O TimingLab 3: Advanced I/O TimingTcl ScriptingLab 4: Tcl ScriptingSmartCompile™ Technology Design Preservation TechniquesLab 5: SmartGuide TechnologyFloorplanning an Effective LayoutLab 6: FloorplanningFPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor \n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 11.1 software. \n\n Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 3: Advanced I/O Timing – Compose timing constraints for an I/O interface. Analyze the timing and determine changes to optimize the interface timing.Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to enhance the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores. \n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_88 DTSTAMP:20090828T204742 DTSTART:20100225T160000Z DTEND:20100227T000000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 11.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 11.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\n Create and edit a User Constraint File (UCF)Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesImplement designs via the Tcl command linePreserve design results by using SmartGuide™ technologyUse the PlanAhead™ tool to create area constraintsChange signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor\n\nCourse Outline\n\n IntroductionLab 1: Timing Closure ReviewUCF EditingLab 2: UCF EditingAdvanced I/O TimingLab 3: Advanced I/O TimingTcl ScriptingLab 4: Tcl ScriptingSmartCompile™ Technology Design Preservation TechniquesLab 5: SmartGuide TechnologyFloorplanning an Effective LayoutLab 6: FloorplanningFPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor \n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 11.1 software. \n\n Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 3: Advanced I/O Timing – Compose timing constraints for an I/O interface. Analyze the timing and determine changes to optimize the interface timing.Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to enhance the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores. \n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_85 DTSTAMP:20090828T203427 DTSTART:20100301T160000Z DTEND:20100303T000000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsTiming Groups and OFFSET ConstraintsPath-Specific Timing ConstraintsLab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\n\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_57 DTSTAMP:20090727T204619 DTSTART:20100303T160000Z DTEND:20100306T000000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT FPGA or Virtex®-6 LXT or SXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGAEffectively utilize the following features of the GTP/GTX:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalizationUse the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a designAccess appropriate reference material for board design issues involving the power supply, reference clocking, and trace design\n\nCourse Outline\n\nDay 1\n\nCourse Agenda and IntroductionSpartan-6 and Virtex-6 Family OverviewTransceiver OverviewTransceiver Clocking and Resets8B/10B Encoder and Decoder Lab 1: 8B/10B Disparity and BypassCommas and Deserializer Alignment Lab 2: Commas and Data Alignment\n\nDay 2\n\nRX Elastic Buffer and Clock CorrectionLab 3: Clock CorrectionChannel Bonding Lab 4: Channel BondingGTP Wizard OverviewLab 5: GTP Core GenerationTransceiver Implementation and SimulationLab 6: Implementation and SimulationPhysical Media Attachments\n\nDay 3\n\nVirtex-6 FPGA 64B/66B Encoding and the GearboxLab 7: GTX 64B/66B EncodingTransceiver Board Design RocketIO Transceiver Test and DebuggingLab 8: System LabRocketIO Transceiver Application Examples\n\nLab Descriptions\n\nLab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.Lab 5: GTP Core Generation – Use the GTP Wizard to create instantiation templates.Lab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design. Lab 7: GTX 64B/66B Encoding – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results.Lab 8: System Lab – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.\n\n\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_102 DTSTAMP:20091202T185105 DTSTART:20100311T160000Z DTEND:20100313T000000Z CATEGORIES:DSP Design SUMMARY:DSP Design Using System Generator DESCRIPTION:This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the System Generator design flow for implementing DSP functionsIdentify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulationList various low-level and high-level functional blocks available in System GeneratorIdentify the high-level blocks available for FIR and FFT designsDesign a multiple-clock-based System Generator systemEmbed two System Generator designs into a larger designUse a custom-designed FPGA PCB as a hardware co-simulation target\n\nCourse Outline\n\nDay 1\n\nIntroduction to System GeneratorSimulink Software BasicsLab 1: Using the Simulink SoftwareBasic Xilinx Design CaptureLab 2: Getting Started with Xilinx System GeneratorSignal RoutingLab 3: Signal RoutingImplementing System ControlLab 4: Implementing System Control\n\nDay 2\n\nMulti-Rate SystemsLab 5: Designing a MAC-Based FIR Filter DesignLab 6: Designing a FIR Filter Using the FIR Compiler Block Xilinx System Generator, Project Navigator, and Platform Studio IntegrationLab 7: System Generator and Project Navigator Integration\n\nLab Descriptions\n\nLab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_83 DTSTAMP:20090828T203122 DTSTART:20100325T150000Z DTEND:20100326T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.\n\n* This course focuses on the Virtex-5, Virtex-6, and Spartan-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the EDK environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse Outline\n\nDay 1\n\nEDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading Software System BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\nInterfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building a Custom IP Peripheral for an Embedded System – PLB v46 Bus Bus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions\n\nBoth the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the Spartan-6 FPGA SP605, Spartan-3E FPGA 1600E, or Virtex-5 FPGA ML507 boards.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design. Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the board.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building a Custom IP Peripheral for an Embedded System – Create and add custom IP (IPIC interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in the design.\n\n\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_110 DTSTAMP:20100203T173735 DTSTART:20100330T150000Z DTEND:20100401T230000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing with VHDL" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_111 DTSTAMP:20100203T175547 DTSTART:20100413T150000Z DTEND:20100415T230000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing with VHDL" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_47 DTSTAMP:20090727T153642 DTSTART:20100420T150000Z DTEND:20100422T230000Z CATEGORIES:Languages SUMMARY:Designing with Verilog DESCRIPTION:This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.\n\nIn this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.After completing this comprehensive training, you will have the necessary skills to: \n\n Write RTL Verilog code for synthesisWrite Verilog test fixtures for simulationCreate a Finite State Machine (FSM) by using VerilogTarget and optimize Xilinx FPGAs by using VerilogUse enhanced Verilog file I/O capabilityRun a timing simulation by using Xilinx Simprim librariesCreate and manage designs within the ISE software design environmentDownload to the Spartan®-3E FPGA 1600E demo board \n\nCourse OutlineDay 1\n\n Hardware Modeling OverviewVerilog Language ConceptsModules and PortsLab 1: Building HierarchyIntroduction to TestbenchesLab 2: Verilog Simulation and RTL Verification \n\nDay 2\n\n Verilog Operators and ExpressionsData Flow-Level ModelingLab 3: MemoryVerilog Procedural StatementsLab 4: Clock Divider and Address CounterControlled Operation StatementsLab 5: n-bit Binary Counter and RTL Verification \n\nDay 3\n\nVerilog Tasks and FunctionsAdvanced Language ConceptsLab 6: Timing SimulationFinite State MachinesLab 7: Finite State MachinesTargeting Xilinx FPGAsLab 8: Implement and DownloadAdvanced Verilog TestbenchesLab 9: Using Verilog File I/O\n\nLab Descriptions The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation. \n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Salt Lake City, UT (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_112 DTSTAMP:20100322T164716 DTSTART:20100428T150000Z DTEND:20100429T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Software Development DESCRIPTION:This two-day course introduces you to software design and development for Xilinx embedded processor systems. You will learn the basic tool use and concepts required for the software phase of the design cycle, after the hardware design is completed.\n\nTopics are comprehensive, covering the design and implementation of the software platform for resource access and management. Major topics include device driver development and user application debugging and integration. Practical implementation tips and best practices are also provided throughout to enable you to make good design decisions and keep your design cycles to a minimum. You will have enough practical information to get started developing the software platform for a Xilinx embedded system based on a PowerPC® 440 or MicroBlaze™ processor. \n\nWhile this course includes many of the topics presented in the Embedded Systems Development and Advanced Features and Techniques of Embedded Systems Development courses, the focus is on software development concepts and practices rather than hardware development. Hardware design concepts and procedures are not covered.* This course focuses on the Virtex-5 architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nImplement an effective software design environment for a Xilinx embedded system using the Xilinx SDK toolsWrite a basic user application using the Xilinx Software Development Kit (SDK) and run it on the embedded system Use Xilinx debugger tools to troubleshoot user applicationsApply software techniques to improve operabilityReduce embedded software development time\n\nCourse Outline\n\nDay 1\n\nCourse AgendaProcessors, Peripherals, and ToolsSoftware Platform DevelopmentLab 1: Basic System ImplementationWriting Code in the Xilinx EnvironmentSoftware Development Using SDKLab 2: Application DevelopmentAddress ManagementInterruptsLab 3: Software Interrupts\n\nDay 2\n\nSoftware Platform Download and BootApplication DebuggingLab 4: DebuggingApplication ProfilingLab 5: SDK ProfilingWriting a Custom Device DriverLab 6: Writing a Device DriverAdvanced Services and Operating SystemsProject Management with the Xilinx Design ToolsLab 7: File Systems\n\nLab Descriptions\n\nLab 1: Basic System Implementation – Construct the hardware and software platforms used for the labs. Begin with Base System Builder to create the hardware design. Specify a basic software platform and add a software application to the system.Lab 2: Application Development – Create a simple software application project from source files for a software loop-based stopwatch. Research hardware and software documentation to complete the application; then download it to hardware.Lab 3: Software Interrupts – Replace a software timing loop with an interrupt-driven timer. Add the timer software and write an interrupt handler for the timer. Configure the FPGA, download, and test the application.Lab 4: Debugging – Set up the SDK debug perspective and the previous lab’s stopwatch application for debugging, setting breakpoints, calculating interrupt latency, and stepping through the program’s operation.Lab 5: SDK Profiling – Profile a program, interpret reports, then enable cache and rewrite code to archive optimal performance.Lab 6: Writing a Device Driver – Create the skeleton driver framework, add an LCD device driver to the BSP, and verify proper device driver operation via a download to hardware test.Lab 7: External Memory Controllers and File Systems – Implement a standalone software platform that incorporates the XilMFS memory file system. Develop an application that performs file-related tasks on external memory.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_60 DTSTAMP:20090727T210733 DTSTART:20100518T150000Z DTEND:20100520T230000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:\n\nThis comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. \n\nIn this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.\n\n\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nImplement the VHDL portion of coding for synthesisIdentify the differences between behavioral and structural coding stylesDistinguish coding for synthesis versus coding for simulationUse scalar and composite data types to represent informationUse concurrent and sequential control structure to regulate information flowImplement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)Simulate a basic VHDL designWrite a VHDL testbench and identify simulation-only constructsIdentify and implement coding best practicesOptimize VHDL code to target specific silicon resources within the Xilinx FPGACreate and manage designs within the ISE software environment\n\nCourse Outline\n\nDay 1\n\nThe “Shape” of VHDLLab 1: Using the ToolsDocumentation in VHDLData TypesConcurrent OperationsLab 2: Using Concurrent StatementsProcesses and VariablesLab 3: Designing a Simple Process\n\nDay 2\n\nIntroduction to TestbenchesISim Simulation Tool BasicsLab 4: Simulating a Simple DesignCreating MemoryLab 5: Building a Dual-Port MemoryFinite State MachinesLab 6: Building a Moore Finite State MachineTargeting Xilinx FPGAsLab 7: Xilinx Tool Flow\n\nDay 3\n\nLoops and Conditional ElaborationLab 8: Using LoopsAttributesFunctions and ProceduresPackages and LibrariesLab 9: Building Your Own PackageInteracting with the SimulationWriting a Good TestbenchLab 10: Building a Meaningful Testbench\n\nLab Descriptions\n\nThe labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Houston, TX (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_118 DTSTAMP:20100506T171004 DTSTART:20100526T150000Z DTEND:20100527T230000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGAEffectively utilize the following features of the GTP/GTX:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalizationUse the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a designAccess appropriate reference material for board design issues involving the power supply, reference clocking, and trace design\n\nCourse Outline\n\nSpartan-6 and Virtex-6 Family OverviewTransceiver Overview (GTP, GTX, GTH)Transceiver Clocking and Resets8B/10B Encoder and Decoder Lab 1: 8B/10B Disparity and BypassCommas and Deserializer Alignment Lab 2: Commas and Data AlignmentRX Elastic Buffer and Clock CorrectionLab 3: Clock CorrectionChannel Bonding Lab 4: Channel BondingTransceiver Wizard OverviewLab 5: GTP WizardImplementing and Simulating a Transceiver DesignLab 6: Implementation and SimulationPhysical Media Attachments64B/66B Encoding and the GearboxLab 7: 64B/66B GTX TransceiverTransceiver-Specific Board Design ConsiderationsRocketIO Transceiver Test and DebuggingLab 8: System LabRocketIO Transceiver Application Examples\n\nLab Descriptions\n\nLab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.Lab 5: GTP Wizard – Use the GTP Wizard to create instantiation templatesLab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design. Lab 7: 64B/66B GTX Transceiver – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results. Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Avnet Electronics Marketing (9601 Amberglen Blvd. Suite 250, Austin, TX 78729) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_119 DTSTAMP:20100601T191450 DTSTART:20100616T150000Z DTEND:20100616T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the I/O Planner to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_138 DTSTAMP:20100611T154211 DTSTART:20100621T150000Z DTEND:20100622T230000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing with Multi-Gigabit Serial I/O" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_139 DTSTAMP:20100611T154245 DTSTART:20100628T150000Z DTEND:20100630T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing for Performance" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_123 DTSTAMP:20100601T193050 DTSTART:20100715T150000Z DTEND:20100716T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsPath-Specific Timing Constraints, Part 1Path-Specific Timing Constraints, Part 2Lab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_126 DTSTAMP:20100601T194648 DTSTART:20100726T150000Z DTEND:20100727T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the Spartan®-6 and Virtex®-6 FPGAs.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nCreate and edit a User Constraint File (UCF)Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesImplement designs via the Tcl command linePreserve design results by using SmartGuide™ technology Use the PlanAhead™ tool to create area constraintsChange signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor\n\nCourse Outline\n\nIntroductionLab 1: Timing Closure Review UCF EditingLab 2: UCF EditingAdvanced I/O TimingLab 3: Advanced I/O TimingTcl ScriptingLab 4: Tcl ScriptingSmartGuide Technology Lab 5: SmartGuide TechnologyFloorplanning an Effective LayoutLab 6: Floorplanning FPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor\n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 12.1 software. \n\nLab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_125 DTSTAMP:20100601T193339 DTSTART:20100729T150000Z DTEND:20100730T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced FPGA Implementation DESCRIPTION:Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the Spartan®-6 and Virtex®-6 FPGAs.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nCreate and edit a User Constraint File (UCF)Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfacesImplement designs via the Tcl command linePreserve design results by using SmartGuide™ technology Use the PlanAhead™ tool to create area constraintsChange signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor\n\nCourse Outline\n\nIntroductionLab 1: Timing Closure Review UCF EditingLab 2: UCF EditingAdvanced I/O TimingLab 3: Advanced I/O TimingTcl ScriptingLab 4: Tcl ScriptingSmartGuide Technology Lab 5: SmartGuide TechnologyFloorplanning an Effective LayoutLab 6: Floorplanning FPGA Editor: Viewing and Editing a Routed DesignLab 7: Advanced FPGA Editor\n\nLab DescriptionsNote: Labs will be based on Xilinx ISE 12.1 software. \n\nLab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.Lab 6: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:BP Sales (11130 Jollyville Rd, Suite 200, Austin, TX 78759) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_130 DTSTAMP:20100601T201848 DTSTART:20100804T150000Z DTEND:20100804T230000Z CATEGORIES:FPGA Design SUMMARY:Essential Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and a demonstration.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun DRC and SSN noise analysisIntegrate IP with the PlanAhead toolImport HDL sources, elaborate, and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics and timingUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse Outline\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsCORE Generator Tool IntegrationLab 3: CORE Generator Tool IntegrationProject Navigator Integration Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead tool so that you can synthesize, add timing constraints, implement, perform timing analysis, and generate a bitstream. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PlanAhead tool’s pin planning environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, make clock logic placement, and make pin assignments.Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator tool with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_134 DTSTAMP:20100601T203105 DTSTART:20100805T150000Z DTEND:20100806T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable performance by using the PlanAhead™ software tool. Topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demonstrations.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentRun the RTL Design Rule Checker (DRC)Import HDL sources and elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placement, and timing critical pathsInsert ChipScope Pro tool debug coresFloorplan the design to improve performance and maintain successful implementation results\n\nCourse Outline\n\nDay 1\n\nPlanAhead Software ReviewLab 1: PlanAhead Software ReviewRTL Development and AnalysisLab 2: RTL Design AnalysisPblocksFloorplanning Techniques Lab 3: Design Analysis and Floorplanning for Performance\n\nDay 2\n\nDesign Preservation with PartitionsLab 4: Leveraging Design Preservation for Predictable Results Debugging with the ChipScope Pro Tool and PlanAhead SoftwareLab 5: Debugging with the ChipScope Pro ToolCourse Summary\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: PlanAhead Software Review – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: RTL Design Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).Lab 3: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 4: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.Lab 5: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_140 DTSTAMP:20100719T144701 DTSTART:20100816T150000Z DTEND:20100818T230000Z CATEGORIES:Languages SUMMARY:Designing with VHDL DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Designing with VHDL" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_141 DTSTAMP:20100719T144853 DTSTART:20100819T150000Z DTEND:20100819T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Custom On-Site Training is available when public Xilinx instructor-led courses do not meet your company's specific training needs.\n\n Private classes can be delivered either at your location or in a nearby facility. Benefits of private classes include: \n\nReduced travel time and costsAbility to control the pace of the classExclusive access to a Xilinx instructorAbility to discuss issues with your peersAbility to discuss confidential issues (under NDA)\n\nFaster Technology can deliver any of our public classes in a private setting for up to 16 students per class for a fixed rate of $6000 USD or 60 training credits per day. \n\nLevel: Any levelCourse Duration: Customer specifiedPrice: $6000 or 60 Xilinx Training Credits per dayCourse Part Number: PRIV23000-11-ILT Who Should Attend?: Companies that have specific training needs that are not met by public Xilinx instructor-led courses.Registration: Request a Private Class \n\nPrivate Class Request Turnaround Time:\n\n Depending on circumstances, it may take up to one month from the time a request is received to the date of the actual class, however, we will do our best to get your class on the schedule as soon as possible. If your class request is for an onsite class, you can speed up the processing of your request by ensuring the room you want to book is available for the specified dates, the students who should attend are available for the specified dates, and providing an IT contact in your comments.\n\nTo request a private on-site class, inquire about course offerings, or any other specific Xilinx training needs, please contact Faster Technology through our Request a Private Class page. LOCATION:Customer On-Site ORGANIZER;CN="Browse for other "Essentials of FPGA Design" classes in our online store": END:VEVENT BEGIN:VEVENT UID:_1_145 DTSTAMP:20100802T192133 DTSTART:20100908T150000Z DTEND:20100908T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the I/O Planner to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_122 DTSTAMP:20100601T192848 DTSTART:20100909T150000Z DTEND:20100910T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsPath-Specific Timing Constraints, Part 1Path-Specific Timing Constraints, Part 2Lab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_146 DTSTAMP:20100802T192639 DTSTART:20100913T150000Z DTEND:20100915T230000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGAEffectively utilize the following features of the GTP/GTX:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalizationUse the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a designAccess appropriate reference material for board design issues involving the power supply, reference clocking, and trace design\n\nCourse Outline\n\nSpartan-6 and Virtex-6 Family OverviewTransceiver Overview (GTP, GTX, GTH)Transceiver Clocking and Resets8B/10B Encoder and Decoder Lab 1: 8B/10B Disparity and BypassCommas and Deserializer Alignment Lab 2: Commas and Data AlignmentRX Elastic Buffer and Clock CorrectionLab 3: Clock CorrectionChannel Bonding Lab 4: Channel BondingTransceiver Wizard OverviewLab 5: GTP WizardImplementing and Simulating a Transceiver DesignLab 6: Implementation and SimulationPhysical Media Attachments64B/66B Encoding and the GearboxLab 7: 64B/66B GTX TransceiverTransceiver-Specific Board Design ConsiderationsRocketIO Transceiver Test and DebuggingLab 8: System LabRocketIO Transceiver Application Examples\n\nLab Descriptions\n\nLab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.Lab 5: GTP Wizard – Use the GTP Wizard to create instantiation templatesLab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design. Lab 7: 64B/66B GTX Transceiver – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results. Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_143 DTSTAMP:20100719T212859 DTSTART:20100914T150000Z DTEND:20100914T203000Z CATEGORIES:General SUMMARY:RTECC Austin DESCRIPTION:The Real-Time & Embedded Computing Conference (RTECC) is a single-day conference and exhibition showcase focused for people that are developing computer systems and time-critical applications serving multiple industries; this includes: industrial control, data communication and telephony, military and aerospace, instrumentation, consumer electronics, image processing, process control, vehicular control and maintenance, embedded appliances and more. \n\nRTECC is suited to meet the needs of Software and Hardware Engineers, both design and Production, R&D, Electrical and Electronic Engineers, Project Engineers, Directors and Managers of Engineering by design. The table-top product showcase is arranged for easy vendor and product comparisons. The open-door technical seminars and workshops allow attendees a valuable learning opportunity and time to talk in depth with technical experts.\n\nRTECC events bring core emerging technologies - the top subjects on the minds of developers, to over 30 cities around the world. Every event is arranged to meet and exchange ideas with the best and brightest in the industry. LOCATION:Austin Marriott North Hotel ORGANIZER;CN="The Real-Time & Embedded Computing Conferences": END:VEVENT BEGIN:VEVENT UID:_1_144 DTSTAMP:20100720T131417 DTSTART:20100916T143000Z DTEND:20100916T200000Z CATEGORIES:General SUMMARY:RTECC Dallas DESCRIPTION:The Real-Time & Embedded Computing Conference (RTECC) is a single-day conference and exhibition showcase focused for people that are developing computer systems and time-critical applications serving multiple industries; this includes: industrial control, data communication and telephony, military and aerospace, instrumentation, consumer electronics, image processing, process control, vehicular control and maintenance, embedded appliances and more. \n\nRTECC is suited to meet the needs of Software and Hardware Engineers, both design and Production, R&D, Electrical and Electronic Engineers, Project Engineers, Directors and Managers of Engineering by design. The table-top product showcase is arranged for easy vendor and product comparisons. The open-door technical seminars and workshops allow attendees a valuable learning opportunity and time to talk in depth with technical experts.\n\nRTECC events bring core emerging technologies - the top subjects on the minds of developers, to over 30 cities around the world. Every event is arranged to meet and exchange ideas with the best and brightest in the industry. LOCATION:Renaissance Dallas Richardson Hotel ORGANIZER;CN="The Real-Time & Embedded Computing Conferences": END:VEVENT BEGIN:VEVENT UID:_1_148 DTSTAMP:20100802T193552 DTSTART:20100923T150000Z DTEND:20100924T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsPath-Specific Timing Constraints, Part 1Path-Specific Timing Constraints, Part 2Lab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Salt Lake City, UT (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_131 DTSTAMP:20100601T201948 DTSTART:20100928T150000Z DTEND:20100928T230000Z CATEGORIES:FPGA Design SUMMARY:Essential Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and a demonstration.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun DRC and SSN noise analysisIntegrate IP with the PlanAhead toolImport HDL sources, elaborate, and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics and timingUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse Outline\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsCORE Generator Tool IntegrationLab 3: CORE Generator Tool IntegrationProject Navigator Integration Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead tool so that you can synthesize, add timing constraints, implement, perform timing analysis, and generate a bitstream. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PlanAhead tool’s pin planning environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, make clock logic placement, and make pin assignments.Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator tool with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_135 DTSTAMP:20100601T203146 DTSTART:20100929T150000Z DTEND:20100930T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable performance by using the PlanAhead™ software tool. Topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demonstrations.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentRun the RTL Design Rule Checker (DRC)Import HDL sources and elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placement, and timing critical pathsInsert ChipScope Pro tool debug coresFloorplan the design to improve performance and maintain successful implementation results\n\nCourse Outline\n\nDay 1\n\nPlanAhead Software ReviewLab 1: PlanAhead Software ReviewRTL Development and AnalysisLab 2: RTL Design AnalysisPblocksFloorplanning Techniques Lab 3: Design Analysis and Floorplanning for Performance\n\nDay 2\n\nDesign Preservation with PartitionsLab 4: Leveraging Design Preservation for Predictable Results Debugging with the ChipScope Pro Tool and PlanAhead SoftwareLab 5: Debugging with the ChipScope Pro ToolCourse Summary\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: PlanAhead Software Review – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: RTL Design Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).Lab 3: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 4: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.Lab 5: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_115 DTSTAMP:20100317T123955 DTSTART:20100930T150000Z DTEND:20101001T230000Z CATEGORIES:DSP Design SUMMARY:DSP Design Using System Generator DESCRIPTION:This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the System Generator design flow for implementing DSP functionsIdentify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulationList various low-level and high-level functional blocks available in System GeneratorUse custom boards for hardware co-simulationIdentify the high-level blocks available for FIR and FFT designsDesign a multiple-clock-based System Generator systemEmbed two System Generator designs into a larger design\n\nCourse Outline\n\nDay 1\n\nIntroduction to System GeneratorSimulink Software BasicsLab 1: Using the Simulink SoftwareBasic Xilinx Design CaptureLab 2: Getting Started with Xilinx System GeneratorSignal RoutingLab 3: Signal RoutingImplementing System ControlLab 4: Implementing System Control\n\nDay 2\n\nMulti-Rate SystemsLab 5: Designing a MAC-Based FIR Filter DesignLab 6: Designing a FIR Filter Using the FIR Compiler Block System Generator, Project Navigator, and Platform Studio IntegrationLab 7: System Generator and Project Navigator IntegrationSpartan-6 and Virtex-6 FPGA DSP PlatformsLab 8: Using System Generator to Develop Virtex-6 and Spartan-6 FPGA DSP Applications\n\nLab Descriptions\n\nLab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.Lab 8: Using System Generator to Develop Virtex-6 and Spartan-6 FPGA DSP Applications – Design a single-carrier Digital Up Converter (DUC) and Digital Down Converter (DDC) to meet WCDMA UTMS 3GPP specifications.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_129 DTSTAMP:20100601T201744 DTSTART:20101006T150000Z DTEND:20101006T230000Z CATEGORIES:FPGA Design SUMMARY:Essential Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and a demonstration.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentAssign I/O pins and clock logicRun DRC and SSN noise analysisIntegrate IP with the PlanAhead toolImport HDL sources, elaborate, and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics and timingUse the PlanAhead tool integrated with the ISE tool Project Navigator environment\n\nCourse Outline\n\nPlanAhead Tool Benefits and Features OverviewLab 1: Getting Started with the PlanAhead ToolI/O Pin and Clock PlanningLab 2: Assigning I/O PinsCORE Generator Tool IntegrationLab 3: CORE Generator Tool IntegrationProject Navigator Integration Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead tool so that you can synthesize, add timing constraints, implement, perform timing analysis, and generate a bitstream. Also introduces the PlanAhead tool environment and views.Lab 2: Assigning I/O Pins – Introduces the PlanAhead tool’s pin planning environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, make clock logic placement, and make pin assignments.Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator tool with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Austin, TX (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_133 DTSTAMP:20100601T203011 DTSTART:20101007T150000Z DTEND:20101008T230000Z CATEGORIES:FPGA Design SUMMARY:Advanced Design with the PlanAhead Analysis and Design Tool DESCRIPTION:Learn to increase design performance and achieve repeatable performance by using the PlanAhead™ software tool. Topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demonstrations.\n\nAfter completing this comprehensive training, you will have the necessary skills to: \n\nUse the PlanAhead tool features and benefitsImport designs into the PlanAhead tool project environmentRun the RTL Design Rule Checker (DRC)Import HDL sources and elaborate and analyze the RTL netlistImplement the design with different implementation strategiesAnalyze design statistics, connectivity, timing, placement, and timing critical pathsInsert ChipScope Pro tool debug coresFloorplan the design to improve performance and maintain successful implementation results\n\nCourse Outline\n\nDay 1\n\nPlanAhead Software ReviewLab 1: PlanAhead Software ReviewRTL Development and AnalysisLab 2: RTL Design AnalysisPblocksFloorplanning Techniques Lab 3: Design Analysis and Floorplanning for Performance\n\nDay 2\n\nDesign Preservation with PartitionsLab 4: Leveraging Design Preservation for Predictable Results Debugging with the ChipScope Pro Tool and PlanAhead SoftwareLab 5: Debugging with the ChipScope Pro ToolCourse Summary\n\nLab Descriptions\n\nNote: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.\n\nLab 1: PlanAhead Software Review – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.Lab 2: RTL Design Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).Lab 3: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.Lab 4: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.Lab 5: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Austin, TX (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_149 DTSTAMP:20100802T194147 DTSTART:20101011T150000Z DTEND:20101011T230000Z CATEGORIES:FPGA Design SUMMARY:Essentials of FPGA Design DESCRIPTION:Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nTake advantage of the primary features of the Spartan-6 FPGAUse the Xilinx Project Navigator to implement and simulate an FPGA designRead reports and determine whether your design goals were metUse the Clocking Wizard to create DCM instantiationsUse the I/O Planner to make good pin assignmentsUse the Xilinx Constraints Editor to enter global timing constraints\n\nCourse Outline\n\nCourse AgendaBasic FPGA ArchitectureXilinx Tool FlowLab 1: Xilinx Tool Flow Reading ReportsLab 2: Clocking Wizard and Pin AssignmentLab 3: Pre-Assigning I/O Pins Using the PlanAhead ToolGlobal Timing ConstraintsLab 4: Global Timing Constraints Synchronous Design TechniquesCourse Summary\n\nLab Descriptions\n\nLab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board.Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_150 DTSTAMP:20100802T194253 DTSTART:20101012T150000Z DTEND:20101013T230000Z CATEGORIES:FPGA Design SUMMARY:Designing for Performance DESCRIPTION:Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAsCreate and integrate cores into your design flow by using the CORE Generator™ software systemDescribe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performanceIncrease performance by duplicating registers and pipeliningIncrease system reliability by adding an appropriate synchronization circuitDescribe different synthesis options and how they can improve performanceDescribe a flow for obtaining timing closure Pinpoint design bottlenecks by using Timing Analyzer reportsApply advanced timing constraints to meet your performance goalsUse advanced implementation options to increase design performance\n\nCourse Outline\n\nDay 1\n\nReview of Essentials of FPGA DesignDesigning with FPGA ResourcesCORE Generator Software SystemBasic FPGA Clock ResourcesVirtex-6 and Spartan-6 FPGA Clock ResourcesLab 1: Designing With FPGA ResourcesFPGA Design TechniquesSynthesis TechniquesLab 2: Synthesis Techniques\n\nDay 2\n\nAchieving Timing ClosureLab 3: Review of Global Timing ConstraintsPath-Specific Timing Constraints, Part 1Path-Specific Timing Constraints, Part 2Lab 4: Achieving Timing ClosureAdvanced Implementation OptionsLab 5: Designing for PerformanceLab 6: FPGA Editor Demo (optional)ChipScope Pro Software (optional)Lab 7: ChipScope Pro Software (optional)\n\nLab Descriptions\n\nLab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.\n\nRegister Today Registration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_151 DTSTAMP:20100802T194422 DTSTART:20101013T150000Z DTEND:20101015T230000Z CATEGORIES:Connectivity SUMMARY:Designing with Multi-Gigabit Serial I/O DESCRIPTION:Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.\n\n* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGAEffectively utilize the following features of the GTP/GTX:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalizationUse the GTP/GTX Transceiver Wizard to instantiate GTP/GTX primitives in a designAccess appropriate reference material for board design issues involving the power supply, reference clocking, and trace design\n\nCourse Outline\n\nSpartan-6 and Virtex-6 Family OverviewTransceiver Overview (GTP, GTX, GTH)Transceiver Clocking and Resets8B/10B Encoder and Decoder Lab 1: 8B/10B Disparity and BypassCommas and Deserializer Alignment Lab 2: Commas and Data AlignmentRX Elastic Buffer and Clock CorrectionLab 3: Clock CorrectionChannel Bonding Lab 4: Channel BondingTransceiver Wizard OverviewLab 5: GTP WizardImplementing and Simulating a Transceiver DesignLab 6: Implementation and SimulationPhysical Media Attachments64B/66B Encoding and the GearboxLab 7: 64B/66B GTX TransceiverTransceiver-Specific Board Design ConsiderationsRocketIO Transceiver Test and DebuggingLab 8: System LabRocketIO Transceiver Application Examples\n\nLab Descriptions\n\nLab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.Lab 5: GTP Wizard – Use the GTP Wizard to create instantiation templatesLab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design. Lab 7: 64B/66B GTX Transceiver – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results. Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_147 DTSTAMP:20100802T193028 DTSTART:20101018T150000Z DTEND:20101019T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.\n\n* This course focuses on the Spartan-6, Virtex-5, and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the Project Navigator environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse Outline\n\nDay 1\n\nEDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading Software System BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\nInterfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building Custom IP for an Embedded System – PLB v46 Bus Bus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions\n\nBoth the MicroBlaze and PowerPC 440 processors are supported in the labs.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design. Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 using the SDK tools to create a software BSP and sample application. Configure the FPGA and download the application.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building Custom IP for an Embedded System – Create and add a custom PLB bus peripheral (LCD interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in an ISE design project.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_153 DTSTAMP:20100802T195227 DTSTART:20101021T150000Z DTEND:20101022T230000Z CATEGORIES:Embedded Design SUMMARY:Embedded Systems Development DESCRIPTION:Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.\n\n* This course focuses on the Spartan-6, Virtex-5, and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nDescribe the various tools that encompass the Xilinx Embedded Development Kit (EDK)Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug softwareCreate and integrate your own IP into the Project Navigator environmentSimulate your own custom peripherals with Bus Functional Models (BFMs)\n\nCourse Outline\n\nDay 1\n\nEDK OverviewBase System BuilderLab 1: Hardware Construction with the Base System BuilderSoftware Development Using SDKLab 2: Adding and Downloading Software System BusesProcessor BasicsInterruptsAdding Hardware to an Embedded DesignLab 3: Adding IP to a Hardware Design\n\nDay 2\n\nInterfacing to the Processor SystemDesigning Your Own Peripheral Using the IPIC InterfaceInstalling Your Own Peripheral Using the IPIC InterfaceLab 4: Building Custom IP for an Embedded System – PLB v46 Bus Bus Functional Model SimulationLab 5: BFM SimulationAdding Your Own IP to the Embedded SystemLab 6: Integrating a Custom Peripheral\n\nLab Descriptions\n\nBoth the MicroBlaze and PowerPC 440 processors are supported in the labs.\n\nLab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design. Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 using the SDK tools to create a software BSP and sample application. Configure the FPGA and download the application.Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.Lab 4: Building Custom IP for an Embedded System – Create and add a custom PLB bus peripheral (LCD interface) to your design by using the Create or Import Peripheral Wizard.Lab 5: BFM Simulation – Use the ModelSim simulator to perform Bus Functional Model simulation to verify functionality of the LCD bus peripheral added in the preceding lab.Lab 6: Integrating a Custom Peripheral – Put it all together: add custom IP to the processor system, then integrate the processor sub-system with other logic in an ISE design project.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Salt Lake City, UT (TBD) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_137 DTSTAMP:20100601T203954 DTSTART:20101025T150000Z DTEND:20101026T230000Z CATEGORIES:Connectivity SUMMARY:Designing a LogiCORE PCI Express System DESCRIPTION:Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system with supporting logic and example designs. With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the Spartan®-6 FPGA PCIe Integrated Endpoint block.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nConstruct a basic PCIe system by:Selecting the appropriate core for your applicationSpecifying requirements of an endpoint applicationConnecting this endpoint with the coreUtilizing FPGA resources to support the coreSimulating the designIdentify the advanced capabilities of the PCIe specification protocol and feature set\n\nCourse Outline\n\nDay 1\n\nCourse Introduction Introduction to the PCIe ArchitectureReview of the PCIe ProtocolPCIe and the CORE Generator™ ToolLab 1: Constructing the PCIe CoreSimulating a PCIe System DesignConnecting Logic to the Core – Local Link Memory Read and Memory Write Completion Details Lab 2: Downstream Port Model Simulation Endpoint Application Considerations Lab 3: Pseudo-Transactional Modeling\n\nDay 2\n\nApplication Focus: DMA Lab 4: Design Implementation Virtex-6 FPGA Root Port Compliance and Debugging Lab 5: Debugging the PCIe Core with the ChipScope Pro Tools Errors and Interrupts Course Summary Appendix: Mechanicals, Hot Plug, and Power\n\nLab Descriptions\n\nLab 1: Constructing the PCIe Core – This lab familiarizes you with all the necessary flow of the Xilinx CORE Generator™ tool for generating a Xilinx LogiCORE Endpoint Block IP. You will select appropriate parameters for the CORE Generator tool and create the PCIe core used throughout the labs.Lab 2: Downstream Port Model Simulation – This lab demonstrates how timing and behavior of a typical link negotiation using the ISim tool. You will observe and capture the effects of link training and write packets to the endpoint application for later use.Lab 3: Pseudo-Transactional Modeling – This lab illustrates pseudo-transactional modeling, which provides various packets to the user design without the need to simulate the PCIe cores themselves.Lab 4: Design Implementation – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream. Lab 5: Debugging the PCIe Core with the ChipScope Pro Tools – This lab illustrates how to use the ChipScope™ Pro tools to monitor the behavior of the core and the endpoint application for proper operation.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (1951 South Fordham Street, Longmont. CO, 80503) ORGANIZER;CN="Register online in our secure store": END:VEVENT BEGIN:VEVENT UID:_1_154 DTSTAMP:20100802T195451 DTSTART:20101027T150000Z DTEND:20101028T230000Z CATEGORIES:Embedded Design SUMMARY:Advanced Embedded Systems Development DESCRIPTION:Advanced Features and Techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system. This course builds on the skills gained in the Embedded Systems Development course. Labs provide hands-on experience with the development, verification, debugging, and simulation of an embedded system. Labs use the Spartan®-6 FPGA SP605 or Virtex®-5 FPGA ML507 demo boards in which designs are downloaded and verified.\n\n* This course focuses on the Spartan-6, Virtex-5, and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.\n\nAfter completing this comprehensive training, you will have the necessary skills to:\n\nAssemble an advanced embedded systemTake advantage of the various Virtex and Spartan FPGA and PowerPC 440 and MicroBlaze processor features, including the crossbar and multi-port memory controllerApply advanced debugging techniques, including the use of the ChipScope™ tool for debugging an embedded system and HDL system simulation of processor-based designsIdentify the steps involved in integrating a memory controller into an embedded system using the PowerPC 440 and the MicroBlaze processorsIntegrate an interrupt controller and interrupt handler into your embedded designDesign a Flash memory-based system and boot load from off-chip Flash memory Perform HDL-based system simulation\n\nCourse Outline\n\nDay 1\n\nEmbedded Systems Development ReviewLab 1: Building a Complete Embedded SystemPowerPC 440 Processor CrossbarDebugging Using the ChipScope Pro AnalyzerLab 2: Debugging Using the ChipScope Pro AnalyzerBlock RAM Memory ControllersMulti-Channel External Memory Controller for Static MemoryPowerPC 440 Processor DDR2 Memory Controller for the Crossbar MCIMulti-Port Memory Controller for Dynamic RAMLab 3: Instantiating a DDR Memory Controller\n\nDay 2\n\nInterruptsFast Simplex LinksAdvanced Processor and Peripheral Interface OptionsLab 4: Interfacing an Embedded System to FPGA FabricAdvanced Processor ConfigurationsBoot LoaderLab 5: Boot Loading from Flash MemoryHDL System Simulation in XPSLab 6: Simulating an Embedded Processor System\n\nLab Descriptions\n\nLab 1: Building a Complete Embedded System – Develop hardware that incorporates IP cores to interface to push buttons, a rotary switch, LEDs, an LCD display, and serial communication. Use the SDK development tools to create an embedded software application project for the hardware built. Lab 2: Debugging Using the ChipScope Pro Analyzer – Perform simultaneous hardware and software debugging with the ChipScope™ Pro Analyzer, SDK Debug perspective, and XMD.Lab 3: Instantiating a DDR Memory Controller – Use XPS to instantiate a DDR memory controller. Explore memory device configurations and proper memory controller clocking procedures.Lab 4: Interfacing an Embedded System to FPGA Fabric – Move data between an embedded system and FPGA fabric via an FSL and a dual-port block RAM. Implement an interrupt controller and an interrupt handler.Lab 5: Boot Loading from Flash Memory – Develop an application that is stored in flash memory, load it through a boot loader program, and execute the software from external memory. Lab 6: Simulating an Embedded Processor System – Set up and perform HDL-based simulation on a design that contains an embedded processor system. Explore the tool flow for performing embedded processor simulation as part of a Project Navigator design in the ISE software.\n\nRegister TodayRegistration for this course is available through our Online Store. LOCATION:Xilinx Learning Center (4055 Valley View Lane #200, Dallas, TX, 75244) ORGANIZER;CN="Register online in our secure store": END:VEVENT END:VCALENDAR

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